Datasheet

Genesys 2 FPGA Board Reference Manual
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
Page 13 of 31
On an Ethernet network each node needs a unique MAC address. To this end the Genesys 2 comes with a MAC
address pre-programmed in a special one-time programmable region (OTP Region 1) of the Quad-SPI Flash
8
. This
unique identifier can be read with the OTP Read command (0x4B). The out-of-box Ethernet demo uses the unique
MAC to allow connecting several Genesys 2 boards to the same network.
A downloadable demonstration project can be found on the Genesys 2 Resource Center.
AH14
AF12
AG12
Kintex-7
MDIO
8
MDC
AJ14 RXD0/SELRGV
Realtek RTL8211E
RJ-45 with
magnetics
RXD1/TXDLY
RXD2/AN0AK13
AH11
AJ13 RXD3/AN1
RXCTL/PHY_AD2
RXCAG10
AK11
AJ12 TXD0
TXD1
TXD2AJ11
AK14
AK10 TXD3
TXCTL
TXCAE10
AH24
AK16 INTB
PHYRSTB
25 MHz
Crystal
CKXTAL1
ACT LED (LD10)
LED0/PHY_AD0
LED1/PHY_AD1
LINK LED
(LD9)
CKXTAL2
*Bootstrapping pull-ups and pull-downs not included. See Genesys 2 Schematic instead
Figure 7. Pin connections between the FPGA and the Ethernet PHY.
8 Oscillators/Clocks
The Genesys 2 board includes several oscillators and crystals, of which two are connected to the FPGA. One
differential LVDS 200MHz oscillator is connected to MRCC GPIO pins AD12/AD11 in bank 33. This input clock can
drive MMCMs or PLLs to generate clocks of various frequencies and with known phase relationships that may be
needed throughout a design. Some rules restrict which MMCMs and PLLs may be driven by the 200MHz input