Datasheet

Genesys 2 FPGA Board Reference Manual

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Page 19 of 31

generates a positive number in the Y field, and moving down represents a negative number (the XS and YS bits in

the status byte are the sign bits – a ‘1’ indicates a negative number). The magnitude of the X and Y numbers

represent the rate of mouse movement – the larger the number, the faster the mouse is moving (the XV and YV

bits in the status byte are movement overflow indicators – a ‘1’ means overflow has occurred). If the mouse moves

continuously, the 33-bit transmissions are repeated every 50ms or so. The L and R fields in the status byte indicate

Left and Right button presses (a ‘1’ indicates the button is being pressed).

L R 0 1 XS YS XY YY P X0 X1 X2 X3 X4 X5 X6 X7 P Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 P1 0 1 00 11

Idle state

Start bit

Mouse status byte X direction byte Y direction byte

Stop bit Start bit

Stop bit

Idle state

Stop bit Start bit

Figure 13. Mouse Data Format.

The microcontroller also supports Microsoft Intellimouse-type extensions for reporting back a third axis representing the mouse wheel, as shown

Table 9.

Command

Action

Set stream mode. The mouse responds with "acknowledge" (0xFA) then resets its movement

counters and enters stream mode.

Enable data reporting. The mouse responds with "acknowledge" (0xFA) then enables data

reporting and resets its movement counters. This command only affects behavior in stream

mode. Once issued, mouse movement will automatically generate a data packet.

Disable data reporting. The mouse responds with "acknowledge" (0xFA) then disables data

reporting and resets its movement counters.

Set mouse sample rate. The mouse responds with "acknowledge" (0xFA) then reads one more

byte from the host. This byte is then saved as the new sample rate, and a new “acknowledge”

packet is issued.

Resend. FE directs mouse to re-send last packet.

Reset. The mouse responds with "acknowledge" (0xFA) then enters reset mode.

Table 9. Microsoft Intellimouse type extensions, commands and actions.

12 User USB 2.0

When the fixed USB roles of the Genesys2 are not enough, an on-board USB 2.0 transceiver (PHY) provides

physical layer implementation for any USB 2.0 user-application. It connects to a USB A (J7-bottom row) and a USB

AB micro (J6) receptacle in parallel, enabling device, host, and OTG USB roles without the need for cable adaptors.

Use only one of the connectors at a time, the one fitting the desired USB role.

The transceiver is a TUSB1210 with a UTMI+ low pin interface (ULPI) towards the FPGA. ULPI is a 12-pin SDR

interface clocked at 60 MHz, resulting in the maximum data rate of 480 Mbps. On the Genesys 2 the transceiver

provides the ULPI clock, which is wired to a clock-capable input pin of the FPGA. Figure 14 shows the connection

diagram of the PHY.

The part of the USB 2.0 stack above the physical layer has to be implemented in the FPGA. Xilinx offers an AXI USB

2.0 Device Controller IP that needed separate licensing at the time of writing.