Datasheet

Genesys 2 FPGA Board Reference Manual

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Page 23 of 31

NOTE: The coupled routing and the anti-alias filters might limit the data speeds when used for digital signals.

The XADC core within the Kintex-7 is a dual channel 12-bit analog-to-digital converter capable of operating at 1

MSPS. Either channel can be driven by any of the auxiliary analog input pairs connected to the JXADC header. The

XADC core is controlled and accessed from a user design via the Dynamic Reconfiguration Port (DRP). This includes

access to the temperature sensor and voltage monitors inside the FPGA. For more information on using the XADC

core, refer to the Xilinx document titled “7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1

MSPS Analog-to-Digital Converter User Guide” (ug480

15 High Pin Count FMC Connector

The Genesys 2 includes a FPGA Mezzanine Card (FMC) Standard-conforming carrier card connector that enables

connecting mezzanine modules compliant with the same standard. Genesys 2-based designs can now be easily

extended with custom or off-the-shelf high-performance modules.

The actual connector used is a 400-pin Samtec ASP-134486-01, the high-pin count, 10mm stacking height variant

of the standard. It is fully bonded to the FPGA, with the exception of CLK3_BIDIR. The 80 differential pairs wired to

regular FPGA user I/O pins are grouped into FMC banks: 34 pairs in LA, 24 pairs in HA and 22 pairs in HB. LA and HA

pairs are powered by the Genesys 2 V

ADJ

rail adjustable in the 1.2V-3.3V range. On the other hand, HB signals are

referenced to a voltage rail provided by the FMC mezzanine card (VIO_B_M2C). For this reason, a whole FPGA

bank is dedicated to HB signals exclusively. This bank remains unpowered, and HB signals cannot be used, if no

FMC mezzanine card, or one that does not provide VIO_B_M2C is connected to the Genesys 2.

Thanks to the flexible voltage range supported by the Genesys 2 it allows high compatibility with existing and

future FMC modules. The Genesys 2 opens the door to the full range of I/O standards supported by the Kintex-7

HR (High Range) I/O architecture over the FMC connector.

The pin-out of the FMC connector can be found in the UCF/XDC constraints file available on www.digilentinc.com.

For above-gigabit speed rates, all ten gigabit transceiver lanes and two accompanying clock pairs are wired to GTX

transceiver banks. Kintex-7 transceiver banks group four lanes and two reference clock input together, and are also

called quads.

Each transceiver lane includes a receive pair and a transmit pair. Lanes DP0-DP3 are wired to quad 115. Lanes DP4-

DP7 go to quad 116, along with the two reference clocks GBTCLK0 and GBTCLK1. The last two lanes DP8 and DP9

are connected to quad 117, while the rest of the pins in these three quads are left unused.

Since an MGTREFCLK can be routed to both the quad above and below its own, both reference clocks can be used to clock any channel in the

three quads.

Table 12,

Table 13, and

Table 14 show how the FMC gigabit signals are mapped to pins and GTX primitives. Refer to the 7 Series FPGAs

GTX/GTH Transceivers User Guide (ug476

) for more information.

http://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf

http://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf