Datasheet

Genesys 2 FPGA Board Reference Manual
Copyright Digilent, Inc. All rights reserved.
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Page 24 of 31
Quad
Primitive
Pin type
Pin
FMC signal
115
GTXE2_CHANNEL
X0Y0
MGTXTXP/N0
Y2/Y1
DP0_C2M_P/N
MGTXRXP/N0
AA4/AA3
DP0_M2C_P/N
X0Y1
MGTXTXP/N1
V2/V1
DP1_C2M_P/N
MGTXRXP/N1
Y6/Y5
DP1_M2C_P/N
X0Y2
MGTXTXP/N2
U4/U3
DP2_C2M_P/N
MGTXRXP/N2
W4/W3
DP2_M2C_P/N
X0Y3
MGTXTXP/N3
T2/T1
DP3_C2M_P/N
MGTXRXP/N3
V6/V5
DP3_M2C_P/N
Table 12. Quad 115 pin-out.
Quad
Primitive
Pin type
Pin
FMC signal
116
GTXE2_CHANNEL
X0Y4
MGTXTXP/N0
P2/P1
DP4_C2M_P/N
MGTXRXP/N0
T6/T5
DP4_M2C_P/N
X0Y5
MGTXTXP/N1
N4/N3
DP5_C2M_P/N
MGTXRXP/N1
R4/R3
DP5_M2C_P/N
X0Y6
MGTXTXP/N2
M2/M1
DP6_C2M_P/N
MGTXRXP/N2
P6/P5
DP6_M2C_P/N
X0Y7
MGTXTXP/N3
L4/L3
DP7_C2M_P/N
MGTXRXP/N3
M6/M5
DP7_M2C_P/N
IBUFDS_
GTE2
X0Y2
MGTREFCLKP/N0
L8/L7
GBTCLK0_P/N
X0Y3
MGTREFCLKP/N1
N8/N7
GBTCLK1_P/N
Table 13. Quad 116 pin-out.
Quad
Primitive
Pin type
Pin
FMC signal
117
GTXE2_
CHANNEL
X0Y8
MGTXTXP/N0
K2/K1
DP8_C2M_P/N
MGTXRXP/N0
K6/K5
DP8_M2C_P/N
X0Y9
MGTXTXP/N1
J4/J3
DP9_C2M_P/N
MGTXRXP/N1
H6/H5
DP9_M2C_P/N
Table 14. Quad 117 pin-out.
16 MicroSD Slot
The Genesys 2 provides a microSD slot for both FPGA configuration and user access. The on-board Auxiliary
Function microcontroller shares the SD card bus with the FPGA. Before the FPGA is configured the microcontroller
must have access to the SD card via an SPI interface. Once a bit file is downloaded to the FPGA (from any source),
the microcontroller powers off the SD slot and relinquishes control of the bus. The FPGA design will find the SD
card in an unpowered state.
All of the SD pins on the FPGA are wired to support full SD speeds in native interface mode, as shown in Figure 17.
The SPI interface is also available, if needed. Once control over the SD bus is passed from the microcontroller to
the FPGA, the SD_RESET signal needs to be actively driven low by the FPGA to power the microSD card slot.