Datasheet

Genesys 2 FPGA Board Reference Manual
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
Page 25 of 31
To talk to an SD card, several communication layers need to be implemented in the FPGA. The physical layer
(de)serializes command and data packets over either the SD native or SPI interface. The data link layer should
implement the SD state machine, issuing initialization and read/write commands specific to the SD standard. The
data link layer provides access to raw blocks/sectors on the SD card. To access a formatted card, a file system layer
should abstract sectors into files and directories. On top of the file system layer comes the actual application.
For more information on implementing an SD card controller, refer to the SD card specification available at
www.sdcard.org.
Kintex-7
P28
SD MICRO (J3)
VDD
DAT2
DAT1
CMD
CLK
DAT3
DAT0
CARD_DETECT
3.3V
SD_RESET
R26
T30
R28
R29
R30
P29
AE24
Figure 17. Kintex-7 microSD card connector interface (PIC24 connections not shown).
17 HDMI
The Genesys 2 board contains two buffered HDMI ports: one source port J4 (output), and one sink port J5 (input).
Both ports use HDMI type-A receptacles and include HDMI buffer TMDS141. The buffers work by terminating,
equalizing, conditioning and forwarding the HDMI stream between the connector and FPGA pins.
Both HDMI and DVI systems use the same TMDS signaling standard, directly supported by Kintex-7 user I/O
infrastructure. Also, HDMI sources are backward compatible with DVI sinks and vice versa. Thus, simple passive
adaptors (available at most electronics stores) can be used to drive a DVI monitor or accept a DVI input. The HDMI
receptacle only includes digital signals, so only DVI-D mode is possible.
The 19-pin HDMI connectors include three differential data channels, one differential clock channel five GND
connections, a one-wire Consumer Electronics Control (CEC) bus, a two-wire Display Data Channel (DDC) bus, a Hot
Plug Detect (HPD) signal, a 5V power pin capable of delivering up to 50mA, and one reserved (RES) pin. All are
wired to the FPGA with the exception of RES.
Pin/Signal
J4 (source)
J5 (sink)
Description
FPGA
pin
Description
FPGA
pin
D[2:0]+/-
Data output
Data input
CLK+/-
Clock output
Clock input
CEC
Consumer Electronics Control
bidirectional
Consumer Electronics Control
bidirectional
SCL, SDA
DDC bidirectional
DDC bidirectional
HPD
Hot-plug detect input (inverted,
active-low)
Hot-plug assert output (active-
high)