Datasheet

Genesys 2 FPGA Board Reference Manual

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Page 26 of 31

5V0

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Powers auxiliary signals

Figure 18. HDMI pin description and assignment.

13.1 TMDS signals

HDMI/DVI is a high-speed digital video stream interface using transition-minimized differential signaling (TMDS).

To make proper use of either of the HDMI ports a standard-compliant transmitter or receiver needs to be

implemented in the FPGA. The implementation details are outside the scope of this manual.

13.2 Auxiliary signals

Presence of a sink on the cable is announced on the hot-plug detect (HPD) pin. Whenever a sink is ready and

wishes to announce its presence, it connects the HPD pin to the 5V0 supply pin. On the Genesys 2 this is achieved

by pulling HDMI_RX_HPA high. This signal defaults low. The source reads the HPD pin through an inverting level-

translator, so HDMI_TX_HPD reads low when a sink is present.

The Display Data Channel, or DDC, is a collection of protocols that enable communication between the display

(sink) and graphics adapter (source). The DDC2B variant is based on I

C, the bus master being the source and the

bus slave the sink. When a source detects high level on the HPD pin, it queries the sink over the DDC bus for video

capabilities. It determines whether the sink is DVI or HDMI-capable and what resolutions are supported. Only

afterwards will video transmission begin. Refer to VESA E-DDC specifications

for more information.

The Consumer Electronics Control, or CEC, is an optional protocol that allows control messages to be passed

around an HDMI chain between different products. A common use case is a TV passing control messages

originating from a universal remote to a DVR or satellite receiver. It is a one-wire protocol at 3.3V level connected

to an FPGA user I/O pin. The wire can be controlled in an open-drain fashion allowing for multiple devices sharing a

common CEC wire. Refer to the CEC addendum of HDMI 1.3 or later specifications

for more information.

14 DisplayPort

DisplayPort is a relatively new industry standard for digital display technology. Its advantages over existing

technologies are: higher bandwidth for greater resolutions and color depths, bi-directional auxiliary channel,

variable interface width, and flexible power topologies among others.

DisplayPort defines a high-speed main link carrying audio and video data, an auxiliary channel, and a hot-plug

detect signal. The main link is a unidirectional, high-bandwidth and low-latency channel. It consists of one, two, or

four AC-coupled differential pairs called lanes. Version 1.1 of the standard

defines two link rates: 1.62 and 2.7

Gbps. The lanes carry both data and an embedded clock at the link rate negotiated between Source and Sink,

independent of the resolution and color depth of the video stream. The link rate is de-coupled from the pixel rate,

resulting in a packetized stream. This differentiates DisplayPort from other digital video standards like DVI/HDMI.

Due to the high link rate, the main link can only be implemented on dedicated gigabit transceiver pins of the

Kintex-7 architecture.

http://www.vesa.org

http://www.hdmi.org