Datasheet

Genesys 2 FPGA Board Reference Manual
Copyright Digilent, Inc. All rights reserved.
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Page 28 of 31
Kintex-7
Lane 1
Lane 0
MGT 118
MGTXTXP/N1
MGTXTXP/N0
MGTREFCLK0P/N
Osc
135 MHz
AD17
AD16
AA18
AB18
AUX_P
AUX_N
AD21
HPD
mDP
Source
Lane 3
Lane 2
MGTXTXP/N3
MGTXTXP/N2
Lane 1
Lane 0
MGTXRXP/N1
MGTXRXP/N0
Lane 3
Lane 2
MGTXRXP/N3
MGTXRXP/N2
mDP
Sink
Y19
Y18
AB19
AC19
AUX_P
AUX_N
AE21
HPD
Figure 19. DisplayPort wiring diagram.
The full implementation details of the DisplayPort standard is outside the scope of this document. Refer to the full
specifications published by VESA for more details. DisplayPort Source and Sink IPs can be licensed separately from
Xilinx.
15 OLED
A Univision Technology Inc. UG-2832HSWEG04 is loaded on the Genesys 2. It is a white monochrome, 128 x 32,
0.91” organic LED display matrix bundled with a Solomon Systech SSD1306 display controller. The display data
interface towards the FPGA is a 4-wire serial peripheral interface (SPI). The 4 wires in controller-terminology are
CS#, D/C#, SDIN, and SCLK, but CS# is hard-wired to ground. This adds to the reset and two power control signals
for proper start-up sequencing. The signals are summarized in Table 16.
Signal
Description
Polarity
FPGA pin
RES#
Reset
Active-low
CS#
Chip select (always active)
Active-low
N/A
D/C#
Data (high)/Command (low)
Both
SCLK
Serial Clock
Active-high
SDIN
Serial Data
Active-high
VBAT#
Power enable for internal power supply
Active-low
VDD#
Power enable for digital power
Active-low
Table 16. OLED signal description.