Datasheet

Genesys 2 FPGA Board Reference Manual
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Page 29 of 31
The serial interface is synchronous to SCLK and must conform the timing specifications below. In most cases, a 10
MHz SCLK and data sent on the falling edge should work.
Figure 20. Serial interface timing diagram.
Start-up sequence:
1. Power up VDD by pulling OLED_VDD low. Wait 1ms.
2. Pulse RES# low for at least 3us.
3. Power up VBAT by pulling OLED_VBAT low. Wait 100ms for voltage to stabilize.
4. Clear screen by writing zero to the display buffer.
5. Send “Display On” command (0xAF).
Command function
Command bytes
Charge pump enable
0x8D, 0x14
Set pre-charge period
0xD9, 0xF1
Contrast control
0x81, 0x0F