Datasheet

Genesys 2 FPGA Board Reference Manual
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Page 31 of 31
1. Provide MCLK for the audio codec.
2. Use an I
2
C master controller to configure the core clocking, sample rates, serial interface format and audio
path.
3. Send or receive audio samples over the serial audio data channel for playback or record.
More advanced users might want to try additional features of the ADAU1761. For example, the on-chip SigmaDSP
core can be programmed to do user-defined digital signal processing.
All relevant information can be found in the ADAU1761 data sheet
18
.
ADAU1761
Kintex-7
ADC_SDATA
LRCLK
DAC_SDATA
BCLK
MCLK
AH19
AJ19
AG18
AJ18
AK19
SDA
AF18
SCL
AE19
L/RHP
L/ROUTP
L/RAUX
L/RINN
Headphone Out
Line Out
Line In
Microphone In
Figure 21. Audio signal connections.
Signal Name
FPGA Pin
Pin Function
ADC_SDATA
AH19
Serialized audio resulting from the analog-to-digital conversion (record).
DAC_SDATA
AJ19
Serialized audio is converted to analog by the codec (playback).
BCLK
AG18
Serial data port clock.
LRCLK
AJ18
Serial data port frame clock.
MCLK
AK19
Master clock.
SDA
AF18
I
2
C configuration interface.
SCL
AE19
I
2
C configuration interface.
Table 18. Audio signal description.
18
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