Datasheet

Genesys 2 FPGA Board Reference Manual
Copyright Digilent, Inc. All rights reserved.
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Page 5 of 31
Supply
Circuits
Device
Current (max/typical)
3.3 V
FPGA I/O, USB, FMC, Clocks,
Pmod, Ethernet, SD slot,
Flash, DisplayPort, HDMI
IC42: LTC3855#1
6 A / 0.8 A
1.0 V
FPGA Core
IC30: LTC3866
14 A / 1.2 A
1.8 V
FPGA Auxiliary
IC36: LTC3605
5 A / 1.6 A
1.5 V
DDR3 and FPGA I/O
IC32: LTC3618
2 A / 0.7 A
0.75V
DDR3 termination, reference
IC32: LTC3618
2 A
2.0 V
FPGA Auxiliary I/O for
memory high data rates
3
IC38: LT1762
150 mA
V
ADJ
(1.2-3.3 V)
User I/O, FMC and FPGA I/O
IC37: LTM4618
5A
3.3 V
Audio analog supply
IC12: LT1761
100 mA
5.0 V
USB Host, HDMI
IC42: LTC3855#2
3 A / 0.3 A
MGT 1.0 V
Gigabit Transceivers VCC
IC41: LT3083
2 A
MGT 1.2 V
Gigabit Transceivers VTT
IC39: LTC3026
1.5 A
MGT 1.8 V
Gigabit Transceivers AUX
IC40: LT1762
150 mA
XADC 1.8 V
XADC supply
IC47: LT1761
100 mA
XADC 1.25 V
XADC reference
IC48: LT1790
5 mA
Table 2. Voltage rail power ratings.
The V
ADJ
power rail requires special attention. It is an adjustable rail that powers the FMC mezzanine connector,
user push-buttons, switches, XADC Pmod connector and the FPGA banks connected to these peripherals (banks 15,
16, 17). The feedback pin of the V
ADJ
regulator is connected to a resistor network modifiable by jumper JP6.
Changing its position changes the resistor divider in the feedback loop, thereby changing the voltage on the
regulator’s output. The possible voltages are listed in Figure 2. If JP6 is not set, the V
ADJ
voltage defaults to 1.2 V.
This feature enables setting the V
ADJ
voltage to suit a certain FMC mezzanine card or application. It is
recommended to only change the JP6 position with the power switch in the OFF position.
Please note that for proper voltage levels in digital signals connected to V
ADJ
-powered FPGA banks (ex. user push-
buttons), the correct I/O standard still needs to be set in the design user constraints (XDC or UCF file). See the
schematic and/or the constraints file to determine which signals are in V
ADJ
-powered banks. The provided master
UCF and XDC files assume the default V
ADJ
voltage of 1.2V, declaring LVCMOS12 as the I/O standard for these
signals.
JP6
V
ADJ
= 1.2V
JP6
V
ADJ
= 1.8V
JP6
V
ADJ
= 2.5V
JP6
V
ADJ
= 3.3V
Figure 2. V
ADJ
programmable voltages.
3
See the 7 Series FPGAs SelectIO Resources User Guide (ug471) for details.