Datasheet

Genesys 2 FPGA Board Reference Manual
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
Page 8 of 31
M0
M1
JTAG
Port
USB
Controller
SPI quad-mode
Flash
1x6 JTAG
Header
SPI
Port
Micro-B USB
Connector
(J17)
Kintex-7
DONE
PIC24
Type A USB
Host
Connector
(J7-top)
Slave
Serial
2
6-pin JTAG
Header
(J19)
PROG_B
Micro SD
Connector (J3)
Media Select (JP4)
User I/O
M2
Mode (JP5)
Programming Mode
JP4 JP5
any
Flash
any JTAG
USB
microSD
Figure 5. Genesys 2 Configuration Options.
The FPGA configuration data is stored in files called bitstreams that have the .bit file extension. The ISE or Vivado
software from Xilinx can create bitstreams from VHDL, Verilog, or schematic-based source files (in the ISE toolset,
EDK is used for MicroBlaze embedded processor-based designs).
Bitstreams are stored in volatile SRAM-based memory cells within the FPGA. This data defines the FPGA’s logic
functions and circuit connections, and it remains valid until it is erased by removing board power, by pressing the
reset button attached to the PROG input, or by writing a new configuration file using the JTAG port.
A Kintex-7 325T bitstream is typically 91,548,896 bits long and can take a long time to transfer depending on the
programming mode. The time it takes to program the Genesys 2 can be decreased by compressing the bitstream
before programming, and then allowing the FPGA to decompress the bitstream itself during configuration.
Depending on design complexity, compression ratios of 10x can be achieved. Bitstream compression can be
enabled within the Xilinx tools (ISE or Vivado) to occur during generation. For instructions on how to do this,
consult the Xilinx documentation for the toolset being used. This option is available for all programming modes.
Mode-specific speed-ups are also available. JTAG clock frequency can be set to the maximum supported by the
programming cable in iMPACT/Vivado Hardware Manager. Similarly, the clock frequency for the SPI Flash can be
increased in device properties (Vivado) or bitstream generation options (ISE). The micro-SD and USB mass-storage
device configuration modes already operate at their maximum possible speed.
After being successfully programmed, the FPGA will cause the "DONE" LED (LD14) to illuminate. Pressing the
“PROG” button (BTN2) at any time will reset the configuration memory in the FPGA. After being reset, the FPGA
will immediately attempt to reprogram itself from whatever method has been selected by the programming mode
jumpers.
The following sections provide greater detail about programming the Genesys 2 using the different methods
available.
5.1 JTAG Programming
The Xilinx tools typically communicate with FPGAs using the Test Access Port and Boundary-Scan Architecture,
commonly referred to as JTAG. During JTAG programming, a .bit file is transferred from the PC to the FPGA using