Datasheet

Genesys 2 FPGA Board Reference Manual

Other product and company names mentioned may be trademarks of their respective owners.

Page 9 of 31

the onboard Digilent USB-JTAG circuitry (port J17) or an external JTAG programmer, such as the Digilent JTAG HS2,

attached to port J19. You can perform JTAG programming at any time after the Genesys 2 has been powered on,

regardless of what the mode jumper (JP5) is set to. If the FPGA is already configured, then the existing

configuration is overwritten with the bitstream being transmitted over JTAG. Setting the mode jumper to the JTAG

setting is useful to prevent the FPGA from being configured from any other bitstream source until a JTAG

programming occurs.

Programming the Genesys 2 with an uncompressed bitstream using the on-board USB_JTAG circuitry usually takes

around four seconds with a 30MHz JTAG clock.

JTAG programming can be done using the hardware server in Vivado or the iMPACT tool included with ISE and the

Labtools version of Vivado.

The demonstration project

available on the Genesys 2 Resource Center

provides an in-depth tutorial on how to

program your board.

5.2 Quad-SPI Programming

For the FPGA to be able to configure itself from the SPI Flash, it first needs to be programmed with the bitstream.

This is called indirect programming and is a two-step process controlled by Hardware Manager (Vivado) or iMPACT

(ISE). First, the FPGA is programmed with a design that can program flash devices, and then data is transferred to

the flash device via the FPGA circuit (this complexity is hidden from the user by the Xilinx tools). After the flash

device has been programmed, it can automatically configure the FPGA at a subsequent power-on or reset event as

determined by the mode jumper setting. Programming files stored in the flash device will remain until they are

overwritten, regardless of power-cycle events.

Programming the flash can take as long as four to five minutes, which is mostly due to the lengthy erase process

inherent to the memory technology. Once written however, FPGA configuration can be very fast, less than a

second. Bitstream compression, SPI bus width, and configuration rate are factors controlled by the Xilinx tools that

can affect configuration speed. The on-board flash has a Quad-SPI interface, which supports single (x1), dual (x2)

and quad (x4) modes. The quad mode results in the fastest possible data transfer rate. For it to work, the bitstream

needs to be generated with the x4 bus width option (Vivado device property) and the non-volatile quad

configuration bit in the flash to be enabled. The Genesys 2 is shipped with this bit enabled.

Indirect programming of the flash can be done using the iMPACT tool included with ISE or Hardware Manager of

Vivado. The correct part to be set in the tools is s25fl256xxxxxx0 from the manufacturer Spansion.

5.3 USB Host and Micro SD Programming

You can program the FPGA from a pen drive attached to the USB-Host port (J7-top row) or a microSD card inserted

into J3 by doing the following:

1. Format the storage device (pen drive or microSD card) with a FAT32 file system.

2. Place a single .bit configuration file in the root directory of the storage device.

3. Attach the storage device to the Genesys 2.

4. Set the JP5 Programming Mode jumper on the Genesys 2 to “USB/SD”.

5. Select the desired storage device using JP4.

https://reference.digilentinc.com/learn/programmable-logic/tutorials/genesys-2-programming-guide/start

https://reference.digilentinc.com/reference/programmable-logic/genesys-2/start