Overview The Digilent Genesys 2 board is an advanced, high-performance, ready-to-use digital circuit development platform based on the latest Kintex-7™ Field Programmable Gate Array (FPGA) from Xilinx. With its high-capacity, high-speed FPGA (Xilinx part number XC7K325T-2FFG900C), fast external memories, high-speed digital video ports, and wide expansions options make the Genesys 2 well suited for data and video processing applications. Several built-in peripherals, including Ethernet, audio and USB 2.
• Serial Flash • Five Pmod ports • USB HID Host for mice, keyboards and USB MSD Host for storage The Genesys 2 can be programmed from various sources, like USB thumb drive, microSD, the on-board non-volatile Flash or the on-board USB-JTAG programmer circuit. The Genesys 2 is compatible with Xilinx’s new high-performance Vivado® Design Suite as well as the ISE toolset. Included in the box is a voucher that unlocks the Design Edition of Vivado that is device-locked to the Genesys 2.
Callout Component Description 5 PROG and user reset buttons 6 Power LED 7 Digital Pmods 8 JTAG header 9 User slide switches 10 User LEDs 11 OLED display 12 Dual analog/digital Pmod 13 User pushbuttons 14 FMC HPC 15 Fan header 16 VADJ jumper 17 micro SD slot 18 3.
• Connecting the board to an Ethernet network will acquire link, IP address and become “pingable” at the IPv4 address displayed on the OLED. • Connecting the USB-UART port to a PC and opening a terminal (115200, 8, N, 1) shows status messages. • Pushing BTNU records audio off the microphone input for five seconds and plays it back on the headphone output if BTND is pushed, or line-out if BTNL. Similarly, BTNR starts a recording off the line-in jack. • The LEDs are showing a scanning light bar.
An external power supply can be used by plugging it into the power jack (J27). The supply must use a coax, centerpositive 2.1mm internal-diameter plug, and deliver 12VDC ±5 %. The minimum current rating of the supply depends on the actual design implemented in the FPGA, but at least 3A (i.e., at least 36W) is recommended. For high-power FMC applications a 60W supply is recommended.
position changes the resistor divider in the feedback loop, thereby changing the voltage on the regulator’s output. The possible voltages are listed in Figure 2. If JP6 is not set, the VADJ voltage defaults to 1.2 V. This feature enables setting the VADJ voltage to suit a certain FMC mezzanine card or application. It is recommended to only change the JP6 position with the power switch in the OFF position. Please note that for proper voltage levels in digital signals connected to VADJ-powered FPGA banks (ex.
4. Fan The Genesys 2 comes with a fan and a secondary heat sink pre-installed on the FPGA package heat sink. The fan is powered from the external 12V DC supply rail and controlled by the FPGA. Control is done by the “FAN_EN” signal. Pulling the signal high from the FPGA opens the transistor driving the fan. This pin is pulled high by default. Feedback is obtained on the “FAN_TACH” signal. This generates a pulse with a frequency proportional to the rotation speed of the fan.
4. A programming file can be transferred from a USB mass-storage device (ex. pen drive) attached to the USB HOST port. Figure 5 shows the different options available for configuring the FPGA. An on-board “mode” jumper (JP5) and a media selection jumper (JP4) select between the programming modes. The FPGA configuration data is stored in files called bitstreams that have the .bit file extension.
The Xilinx tools typically communicate with FPGAs using the Test Access Port and Boundary-Scan Architecture, commonly referred to as JTAG. During JTAG programming, a .bit file is transferred from the PC to the FPGA using the onboard Digilent USB-JTAG circuitry (port J17) or an external JTAG programmer, such as the Digilent JTAG HS2, attached to port J19. You can perform JTAG programming at any time after the Genesys 2 has been powered on, regardless of what the mode jumper (JP5) is set to.
• When steadily lit the auxiliary microcontroller is either booting up or currently reading the configuration medium (microSD or pen drive) and downloading a bitstream to the FPGA. • A slow pulse means the microcontroller is waiting for a configuration medium to be plugged in. • In case of an error during configuration the LED will blink rapidly. It could be that the device plugged in is not getting recognized, it is not properly formatted or the bitstream is not compatible with the FPGA.
Setting Value Output driver impedance RZQ/7 Chip Select pin Enabled Rtt (nominal) – On-die termination RZQ/6 Internal Vref Disabled Reference clock Use system clock Internal termination impedance N/A DCI cascade Disabled Table 4. DDR3 settings for the Genesys 2. The MIG Wizard will require the fixed pin-out of the memory signals to be entered and validated before generating the IP core.
7. Ethernet PHY The Genesys 2 board includes a Realtek RTL8211E-VL PHY paired with an RJ-45 Ethernet jack with integrated magnetics to implement a 10/100/1000 Ethernet port for network connection. The PHY interfaces with the FPGA via RGMII for data and MDIO for management. Bank 33 powered at 1.5V is populated with these signals. The auxiliary interrupt (INTB), power management (PMEB) signals are wired to bank 32 and powered at 1.8V.
8. Oscillators/Clocks The Genesys 2 board includes several oscillators and crystals, of which two are connected to the FPGA. One differential LVDS 200MHz oscillator is connected to MRCC GPIO pins AD12/AD11 in bank 33. This input clock can drive MMCMs or PLLs to generate clocks of various frequencies and with known phase relationships that may be needed throughout a design. Some rules restrict which MMCMs and PLLs may be driven by the 200MHz input clock.
Two on-board status LEDs provide visual feedback on traffic flowing through the port: the transmit LED (LD13) and the receive LED (LD12). Signal names that imply direction are from the point-of-view of the DTE (Data Terminal Equipment), in this case the PC. The connections between the FT232R and the FPGA are shown in Figure 8. 10. PC - FPGA Data Transfer (DPTI/DSPI) The Genesys 2 provides two interface types that can be used to transfer user data between a PC and an FPGA design.
provided by the USB controller that is input to the FPGA. In asynchronous mode data transfer is happening on transitions of read and write control signals. The USB controller emulates a FIFO memory, providing status signals about the availability of data to be read or free space for data to be written. The FPGA controls data transfer by read, write and output enable signals. Signal Direction (FPGA) Description D[7:0] I/O Data bus. RXF# Input When low, data is available for reading from the FIFO.
11. USB HID Host The Auxiliary Function microcontroller (Microchip PIC24FJ128) provides the Genesys 2 with USB HID host capability. After power-up, the microcontroller is in configuration mode, either downloading a bitstream to the FPGA, or waiting on it to be programmed from other sources. Once the FPGA is programmed, the microcontroller switches to application mode, which is USB HID Host in this case.
When a keyboard or mouse is connected to the Genesys 2, a “self-test passed” command (0xAA) is sent to the host. After this, commands may be issued to the device. Since both the keyboard and the mouse use the same PS/2 port, one can tell the type of device connected using the device ID. This ID can be read by issuing a Read ID command (0xF2). Also, a mouse sends its ID (0x00) right after the “self-test passed” command, which distinguishes it from a keyboard. 11.2.
clock line is used as a “clear to send” signal. If the host drives the clock line low, the keyboard must not send any data until the clock is released. The keyboard sends data to the host in 11-bit words that contain a ‘0’ start bit, followed by 8-bits of scan code (LSB first), followed by an odd parity bit and terminated with a ‘1’ stop bit. The keyboard generates 11 clock transitions (at 20 to 30 kHz) when the data is sent, and data is valid on the falling edge of the clock. 11.3.
12. User USB 2.0 When the fixed USB roles of the Genesys2 are not enough, an on-board USB 2.0 transceiver (PHY) provides physical layer implementation for any USB 2.0 user-application. It connect to a USB A (J7-bottom row) and a USB AB micro (J6) receptacle in parallel, enabling device, host, and OTG USB roles without the need for cable adaptors. Use only one of the connectors at a time, the one fitting the desired USB role.
The Genesys 2 board includes eight slide switches, six push buttons, and eight individual LEDs. The pushbuttons and slide switches are connected to the FPGA via series resistors to prevent damage from inadvertent short circuits (a short circuit could occur if an FPGA pin assigned to a pushbutton or slide switch was inadvertently defined as an output).
The Genesys 2 features four Pmod connectors of different “styles” with subtle differences between them. Table 10 summarizes these differences. Pmod conector Power Analog/Digital Routing Series protection Recommended usage JXADC VADJ Dual Differential; Pairs: 1-7,2-8,3-9,4-10 100 ohm Analog inputs; LVDS_25 input/output (VADJ=2.5V) JA, JB 3.3 V Digital-only Differential; Pairs: 1-2,3-4,7-8,9-10 0 ohm >=10MHz; LVDS_25 input JC, JD 3.
The on-board Pmod expansion connector labeled “JXADC” is wired to the auxiliary analog input pins of the FPGA. Depending on the configuration, this connector can be used to input differential analog signals to the analog-to-digital converter inside the Kintex-7 (XADC). Any or all pairs in the connector can be configured either as analog input or digital input-output. The Dual Analog/Digital Pmod on the Genesys 2 differs from the rest in the routing of its traces.
pins and GTX primitives. Refer to the 7 Series FPGAs GTX/GTH Transceivers User Guide (ug476 [http://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf]) for more information.
16. MicroSD Slot The Genesys 2 provides a microSD slot for both FPGA configuration and user access. The on-board Auxiliary Function microcontroller shares the SD card bus with the FPGA. Before the FPGA is configured the microcontroller must have access to the SD card via an SPI interface. Once a bit file is downloaded to the FPGA (from any source), the microcontroller powers off the SD slot and relinquishes control of the bus. The FPGA design will find the SD card in an unpowered state.
Pin/Signal J4 (Source) Description J5 (Sink) FPGA Pin Description D[2:0]+/- Data output Data input CLK+/- Clock output Clock input CEC Consumer Electronics Control bidirectional Consumer Electronics Control bidirectional SCL, SDA DDC bidirectional DDC bidirectional HPD Hot-plug detect input (inverted, active-low) Hot-plug assert output (active-high) 5V0 Powered from 5V rail Powers auxiliary signals FPGA Pin Table 15. HDMI pin description and assignment. 13.1.
DisplayPort defines a high-speed main link carrying audio and video data, an auxiliary channel, and a hot-plug detect signal. The main link is a unidirectional, high-bandwidth and low-latency channel. It consists of one, two, or four ACcoupled differential pairs called lanes. Version 1.1 of the standard defines [http://www.vesa.org] two link rates: 1.62 and 2.7 Gbps.
The full implementation details of the DisplayPort standard is outside the scope of this document. Refer to the full specifications published by VESA for more details. DisplayPort Source and Sink IPs can be licensed separately from Xilinx. 15. OLED A Univision Technology Inc. UG-2832HSWEG04 is loaded on the Genesys 2. It is a white monochrome, 128 x 32, 0.91” organic LED display matrix bundled with a Solomon Systech SSD1306 display controller.
Start-up sequence: 1. 2. 3. 4. 5. 6. Power up VDD by pulling OLED_VDD low. Wait 1ms. Pulse RES# low for at least 3us. Send initialization/configuration commands (see Table 17). Power up VBAT by pulling OLED_VBAT low. Wait 100ms for voltage to stabilize. Clear screen by writing zero to the display buffer. Send “Display On” command (0xAF).
Command function Command bytes Scan direction 0xC0 COM pins configuration 0xDA, 0x00 Addressing mode: horizontal 0x20 Table 18. OLED configuration commands. After start-up, writing to the display is done by sending data bytes over the serial interface (D/C# high). Each data bit corresponds to a pixel, with the addressing mode, inversion and scan direction settings determining exactly which. 16.
3. Send or receive audio samples over the serial audio data channel for playback or record. More advanced users might want to try additional features of the ADAU1761. For example, the on-chip SigmaDSP core can be programmed to do user-defined digital signal processing. All relevant information can be found in the ADAU1761 datasheet [http://www.analog.com/media/en/technicaldocumentation/data-sheets/ADAU1761.pdf].
