Datasheet

Setting Value
Output driver impedance RZQ/7
Chip Select pin Enabled
Rtt (nominal) – On-die termination RZQ/6
Internal Vref Disabled
Reference clock Use system clock
Internal termination impedance N/A
DCI cascade Disabled
Table 4. DDR3 settings for the Genesys 2.
The MIG Wizard will require the fixed pin-out of the memory signals to be entered and validated before generating the
IP core. For your convenience an importable UCF/XDC file is provided on the Digilent website to speed up the process.
For more details on the Xilinx memory interface solutions refer to the 7 Series FPGAs Memory Interface Solutions
User
Guide (ug586) [http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_1/ug586_7Series_MIS.pdf].
6.2. Quad-SPI Flash
Non-volatile storage is provided by a Spansion S25FL256S flash memory. FPGA configuration files can be written to it,
and mode settings are available to cause the FPGA to automatically read a configuration from this device at power on. A
Kintex-7 325T configuration file requires just over 10 MiB (mebibyte) of memory, leaving about 70% of the flash device
available for user data. Or, if the FPGA is getting configured from another source, the whole memory can be used for
custom data.
The contents of the memory can be manipulated by issuing certain commands on the SPI bus. The implementation of
this protocol is outside the scope of this document. All signals in the SPI bus except SCK are general-purpose user I/O
pins after FPGA configuration. SCK is an exception because it remains a dedicated pin even after configuration. Access
to this pin is provided through a special FPGA primitive called STARTUPE2. The AXI Quad SPI IP core is
recommended for easy access to the Flash memory.
NOTE: Refer to the manufacturer’s
datasheets
[http://www.spansion.com/Support/Datasheets/S25FL128S_256S_00.pdf] and Xilinx user guides
[http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf] for more information.