Datasheet

7. Ethernet PHY
The Genesys 2 board includes a Realtek RTL8211E-VL PHY paired with an RJ-45 Ethernet jack with integrated
magnetics to implement a 10/100/1000 Ethernet port for network connection. The PHY interfaces with the FPGA via
RGMII for data and MDIO for management. Bank 33 powered at 1.5V is populated with these signals. The auxiliary
interrupt (INTB), power management (PMEB) signals are wired to bank 32 and powered at 1.8V. Both of these signals
are open-drain outputs from the PHY and need internal pull-ups enabled in the FPGA, if they are used. The reset signal
(PHYRSTB) is wired to bank 12, powered at 3.3V. The connection diagram can be seen on Figure 7.
At power-on reset, the PHY is set to the following defaults using the configuration pins in parenthesis:
• Auto-negotiation enabled, advertising all 10/100/1000 modes (AN[1:0])
• PHY address=00001 (PHY_AD[2:0])
• No delay for TXD and RXD relative to TXC and RXC for data latching (RXDLY, TXDLY)
If an Ethernet cable is plugged in, establishing link is attempted straight after power-up, even if the FPGA is not
programmed.
Two status indicator LEDs are on-board near the RJ-45 connector that indicate traffic (LD10) and valid link state (LD9).
The table below shows the default behavior.
Function Designator State Description
ACT LD10 Blinking Transmitting or receiving
LINK LD9 On Link up
Blinking 0.4s ON, 2s OFF Link up, Energy Efficient Ethernet (EEE) mode
Table 5. Ethernet status LEDs.
The on-board PHY implements Layer 1 in the Ethernet stack, interfacing between the physical copper medium and the
media access control (MAC). The MAC must be implemented in the FPGA and mapped to the PHY’s RGMII interface.
Vivado-based design can use the Xilinx AXI Ethernet Subsystem IP core to implement the MAC and wire it to the
processor and the memory subsystem. At the time of writing the IP core needed to be licensed separately.
On an Ethernet network each node needs a unique MAC address. To this end the Genesys 2 comes with a MAC address
pre-programmed in a special one-time programmable region (OTP Region 1) of the Quad-SPI Flash6. This unique
identifier can be read with the OTP Read command (0x4B). The out-of-box Ethernet demo uses the unique MAC to
allow connecting several Genesys 2 boards to the same network.
A downloadable demonstration project can be found on the
Genesys 2 wiki page
[https://reference.digilentinc.com/genesys2:genesys2].