Datasheet

8. Oscillators/Clocks
The Genesys 2 board includes several oscillators and crystals, of which two are connected to the FPGA. One differential
LVDS 200MHz oscillator is connected to MRCC GPIO pins AD12/AD11 in bank 33. This input clock can drive
MMCMs or PLLs to generate clocks of various frequencies and with known phase relationships that may be needed
throughout a design. Some rules restrict which MMCMs and PLLs may be driven by the 200MHz input clock. For a full
description of these rules and of the capabilities of the Kintex-7 clocking resources, refer to the “7 Series FPGAs
Clocking Resources User Guide” (
ug472
[http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf]) available from Xilinx.
Xilinx offers the Clocking Wizard IP core to help users generate the different clocks required for a specific design. This
wizard will properly instantiate the needed MMCMs and PLLs based on the desired frequencies and phase relationships
specified by the user. The wizard will then output an easy to use wrapper component around these clocking resources
that can be inserted into the user’s design. The clocking wizard can be accessed from within the Vivado Block Design or
Core Generator tools.
The second oscillator outputs a differential LVDS 135MHz clock which enters the FPGA on MGTREFCLK pins. This
connects to clock primitives dedicated to the gigabit transceivers and is used for DisplayPort designs.
9. USB UART Bridge (Serial Port)
The Genesys 2 includes an FTDI FT232R USB-UART bridge (attached to connector J15) that lets you use PC
applications to communicate with the board using standard Windows COM port commands. Free USB-COM port
drivers, available from Windows Update or www.ftdichip.com [http://www.ftdichip.com] under the “Virtual Com Port” or
VCP heading, convert USB packets to UART/serial port data. Serial port data is exchanged with the FPGA using a two-
wire serial port (TXD/RXD) with no handshake signals. After the drivers are installed, I/O commands can be used from
the PC directed to the COM port to produce serial data traffic on the Y20 and Y23 FPGA pins.