Datasheet

11. USB HID Host
The Auxiliary Function microcontroller (Microchip PIC24FJ128) provides the Genesys 2 with USB HID host capability.
After power-up, the microcontroller is in configuration mode, either downloading a bitstream to the FPGA, or waiting
on it to be programmed from other sources. Once the FPGA is programmed, the microcontroller switches to application
mode, which is USB HID Host in this case. Firmware in the microcontroller can drive a mouse or a keyboard attached to
the type A USB connector at J7 labeled “USB HID”. J7 is a dual-row USB A receptacle, with the top row connected to
the Auxiliary Function microcontroller. Hub support is not currently available, so only a single mouse or a single
keyboard can be used. The PIC24 drives several signals into the FPGA – two are used to implement a standard PS/2
interface for communication with a mouse or keyboard, and the others are connected to the FPGA’s two-wire serial
programming port, so the FPGA can be programmed from a file stored on a USB pen drive or microSD card.
11.1. HID Controller
The Auxiliary Function microcontroller hides the USB HID protocol from the FPGA and emulates an old-style PS/2
bus. The microcontroller behaves just like a PS/2 keyboard or mouse would. This means new designs can re-use existing
PS/2 IP cores. Mice and keyboards that use the PS/2 protocol use a two-wire serial bus (clock and data) to communicate
with a host. On the Genesys 2, the microcontroller emulates a PS/2 device, while the FPGA plays the role of the host.
Both the mouse and the keyboard use 11-bit words that include a start bit, data byte (LSB first), odd parity, and stop bit,
but the data packets are organized differently, and the keyboard interface allows bi-directional data transfers (so the host
device can illuminate state LEDs on the keyboard). Bus timings are shown in Figure 11.
The clock and data signals are only driven when data transfers occur; otherwise they are held in the idle state at logic ‘1.’
This requires that when the PS/2 signals are used in a design, internal pull-ups must be enabled in the FPGA on the data
and clock pins. The clock signal is normally driven by the device, but may be held low by the host in special cases. The
timings define signal requirements for mouse-to-host communications and bi-directional keyboard communications. A
PS/2 interface circuit can be implemented in the FPGA to create a keyboard or mouse interface.