Datasheet

12. User USB 2.0
When the fixed USB roles of the Genesys2 are not enough, an on-board USB 2.0 transceiver (PHY) provides physical
layer implementation for any USB 2.0 user-application. It connect to a USB A (J7-bottom row) and a USB AB micro (J6)
receptacle in parallel, enabling device, host, and OTG USB roles without the need for cable adaptors. Use only one of the
connectors at a time, the one fitting the desired USB role.
The transceiver is a TUSB1210 with a UTMI+ low pin interface (ULPI) towards the FPGA. ULPI is a 12-pin SDR
interface clocked at 60 MHz, resulting in the maximum data rate of 480 Mbps. On the Genesys 2 the transceiver provides
the ULPI clock, which is wired to a clock-capable input pin of the FPGA. Figure 14 shows the connection diagram of the
PHY.
The part of the USB 2.0 stack above the physical layer has to be implemented in the FPGA. Xilinx offers an AXI USB
2.0 Device Controller IP that needed separate licensing at the time of writing.
Auxiliary circuitry, like an electronic power switch and jumpers are used to implement different USB roles. In Host
applications, the switch can be commanded through the PHY to power VBUS. The switch has built-in current limit and
short circuit protection. VBUS error conditions are signaled to the FPGA by means of a status pin. In Device role, this
switch should be disabled. A jumper (JP1) in series with the power switch can be used to make sure VBUS is not
inadvertently powered. Another jumper (JP2) (dis)connects a 150 µF capacitor to/from the VBUS. Use it to implement
the different bus capacitance requirements of the USB roles.
For more information, refer to the TUSB1210 datasheet [http://www.ti.com/lit/gpn/tusb1210] and the USB 2.0
specifications [http://www.usb.org/developers/docs/usb20_docs].
13. Basic I/O