Datasheet

16. MicroSD Slot
The Genesys 2 provides a microSD slot for both FPGA configuration and user access. The on-board Auxiliary Function
microcontroller shares the SD card bus with the FPGA. Before the FPGA is configured the microcontroller must have
access to the SD card via an SPI interface. Once a bit file is downloaded to the FPGA (from any source), the
microcontroller powers off the SD slot and relinquishes control of the bus. The FPGA design will find the SD card in an
unpowered state.
All of the SD pins on the FPGA are wired to support full SD speeds in native interface mode, as shown in Figure 17.
The SPI interface is also available, if needed. Once control over the SD bus is passed from the microcontroller to the
FPGA, the SD_RESET signal needs to be actively driven low by the FPGA to power the microSD card slot.
To talk to an SD card, several communication layers need to be implemented in the FPGA. The physical layer (de)
serializes command and data packets over either the SD native or SPI interface. The data link layer should implement the
SD state machine, issuing initialization and read/write commands specific to the SD standard. The data link layer
provides access to raw blocks/sectors on the SD card. To access a formatted card, a file system layer should abstract
sectors into files and directories. On top of the file system layer comes the actual application.
For more information on implementing an SD card controller, refer to the SD card specification available at
www.sdcard.org [http://www.sdcard.org].
17. HDMI
The Genesys 2 board contains two buffered HDMI ports: one source port J4 (output), and one sink port J5 (input). Both
ports use HDMI type-A receptacles and include HDMI buffer TMDS141. The buffers work by terminating, equalizing,
conditioning and forwarding the HDMI stream between the connector and FPGA pins.
Both HDMI and DVI systems use the same TMDS signaling standard, directly supported by Kintex-7 user I/O
infrastructure. Also, HDMI sources are backward compatible with DVI sinks and vice versa. Thus, simple passive
adaptors (available at most electronics stores) can be used to drive a DVI monitor or accept a DVI input. The HDMI
receptacle only includes digital signals, so only DVI-D mode is possible.
The 19-pin HDMI connectors include three differential data channels, one differential clock channel five GND
connections, a one-wire Consumer Electronics Control (CEC) bus, a two-wire Display Data Channel (DDC) bus, a Hot
Plug Detect (HPD) signal, a 5V power pin capable of delivering up to 50mA, and one reserved (RES) pin. All are wired
to the FPGA with the exception of RES.