Datasheet

DisplayPort defines a high-speed main link carrying audio and video data, an auxiliary channel, and a hot-plug detect
signal. The main link is a unidirectional, high-bandwidth and low-latency channel. It consists of one, two, or four AC-
coupled differential pairs called lanes. Version 1.1 of the standard defines [http://www.vesa.org] two link rates: 1.62 and 2.7
Gbps. The lanes carry both data and an embedded clock at the link rate negotiated between Source and Sink,
independent of the resolution and color depth of the video stream. The link rate is de-coupled from the pixel rate,
resulting in a packetized stream. This differentiates DisplayPort from other digital video standards like DVI/HDMI. Due
to the high link rate, the main link can only be implemented on dedicated gigabit transceiver pins of the Kintex-7
architecture.
The auxiliary channel is a bidirectional channel for link management and device control. It is AC-coupled, just like the
main link lanes, but uses a different encoding and the lower data rate of 1Mbps. Upon hot-plug detection a Source will
attempt to configure the link through link training. Handshaking link parameters happens via the auxiliary channel.
Genesys 2 includes two Mini DisplayPort (mDP) connectors: one wired as Source, the other as Sink. Both support a
maximum lane count of four on the main link. MGT quad 118 is dedicated to DisplayPort. On-board there is a 135 MHz
reference oscillator mapped to MGTREFCLK0 which should be used to generate the desired link rate. See Table 15 for
pin mapping. Refer to the Xilinx 7 Series FPGAs GTX/GTH Transceivers User Guide (ug47613) for more information
on how to implement high-speed interfaces.
Quad Primitive Pin type Pin DisplayPort signal
118 GTXE2_CHANNEL X0Y12 MGTXTXP/N0 D2/D1 Source Lane 0
MGTXRXP/N0 E4/E3 Sink Lane 0
X0Y13 MGTXTXP/N1 C4/C3 Source Lane 1
MGTXRXP/N1 D6/D5 Sink Lane 1
X0Y14 MGTXTXP/N2 B2/B1 Source Lane 2
MGTXRXP/N2 B6/B5 Sink Lane 2
X0Y15 MGTXTXP/N3 A4/A3 Source Lane 3
MGTXRXP/N3 A8/A7 Sink Lane 3
IBUFDS_ X0Y6 MGTREFCLKP/N0 C8/C7 135 MHz
Table 17. DisplayPort quad pinout.
The auxiliary channel is a bidirectional LVDS bus. Depending on the Xilinx tool/IP version, instantiating a differential
I/O buffer with LVDS signaling standard might not be possible. The work-around is to have two pairs of pins wired and
shorted together as seen in Figure 19. One pair should be implemented as input-only and the other as output-only.
If the tool/IP allows bidirectional LVDS buffers, only one of the pairs needs to be used (it does not matter which), while
the other declared as input and not used.
The hot-plug detect (HPD) signal connects to a general user I/O pin and should be configured as an input.