Datasheet

Command function Command bytes
Scan direction 0xC0
COM pins configuration 0xDA, 0x00
Addressing mode: horizontal 0x20
Table 18. OLED configuration commands.
After start-up, writing to the display is done by sending data bytes over the serial interface (D/C# high). Each data bit
corresponds to a pixel, with the addressing mode, inversion and scan direction settings determining exactly which.
16. Audio Codec
The Genesys 2 board includes an Analog Devices ADAU1
761 SigmaDSP audio codec (IC11) complementing its
multimedia features. Four 1/8” (3.5mm) audio jacks are available for line-out (J11-green), headphone-out (J10-black),
line-in (J13-blue), and microphone-in (J12-pink). Each jack carries two channels of analog audio (stereo), with the
exception of the microphone input, which is mono.
To record or play back audio in an FPGA design, the audio data needs to be converted. The audio codec bridges the gap
between the analog jacks and the digital FPGA pins. Analog-to-digital and digital-to-analog conversion is done at up to
24 bits and 96 kHz sampling rate. Digital audio data is carried to/from the FPGA on a serial, full-duplex interface, which
supports several different formats, the default being I2S. This interface is clocked by the FPGA through BCLK by
default, but the codec can be configured to provide the clock itself.
Configuring the audio codec can be done over I2C. It responds to slave address 0b0111011, followed by a 16-bit register
address and one or more data bytes. These registers control every functional aspect of the codec.
The codec is clocked from the FPGA through the Master Clock (MCLK) pin. A clock must be provided for the codec to
function, including the I2C port. The exact frequency depends on the desired sample rate and whether PLL will be used,
but 12 MHz is a good start. The clocking infrastructure of 7 series FPGA is more than capable of synthesizing the right
frequency from the on-board 100 MHz reference oscillator.
For proper use, the concept of audio paths needs to be understood. Internal to the codec there are two signal paths:
Playback and Record. Both are highly configurable analog paths with mixers and amplifiers that route audio signals
through the chip. The Playback path is the output path that routes audio from different sources like the digital-to-analog
converter or input mixers towards the headphone and line out jacks. On the other hand, the record path routes audio
from the line-in and microphone-in towards the analog-to-digital converters. Having routing elements at every step
enables signal mixing between channels, amplification, muting and bypass. However, it also means that each element has
to be properly configured along the path.
Keep in mind that audio jack designations might differ from codec analog frontend designators. For example, the line-in
jack connects to the AUX port of the codec. The microphone jack is wired to the IN port. Also, notice that although
some ports offer differential amplifiers and signaling, they are not used on the Genesys 2. For example, the OUT port is
differential, comprising 4 pins: LOUTP, LOUTN, ROUTP, and ROUTN. However, the N-side of the differential pairs
is left floating, while the P-side connects to the jack.
At the very least an audio-aware FPGA design should do the following:
1. Provide MCLK for the audio codec.
2. Use an I2C master controller to configure the core clocking, sample rates, serial interface format and audio path.