Datasheet

3. Send or receive audio samples over the serial audio data channel for playback or record.
More advanced users might want to try additional features of the ADAU1761. For example, the on-chip SigmaDSP core
can be programmed to do user-defined digital signal processing.
All relevant information can be found in the ADAU1761 datasheet [http://www.analog.com/media/en/technical-
documentation/data-sheets/ADAU1761.pdf].
Signal Name FPGA Pin Pin Function
ADC_SDATA AH19 Serialized audio resulting from the analog-to-digital conversion (record).
DAC_SDATA AJ19 Serialized audio is converted to analog by the codec (playback).
BCLK AG18 Serial data port clock.
LRCLK AJ18 Serial data port frame clock.
MCLK AK19 Master clock.
SDA AF18 I2C configuration interface.
SCL AE19 I2C configuration interface.
Table 19. Audio signal description.
1)
With the exception of CLK3_BIDIR
2)
See the 7-Series FPGAs SelectIO Resources User Guide (ug471
[http://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf]) for details.
genesys2/refmanual.txt · Last modified: 2015/11/02 18:40 by Martha