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Getting started with Digilent NetFPGA SUME, a Xilinx Virtex 7 FPGA board for

high performance computing and networking systems

Introduction

The NetFPGA project is a group to develop open source hardware and software for rapid

prototyping of high-speed, hardware-accelerated networking systems. The NetFPGA project is

enabled by Field Programmable Gate Array (FPGA) technology so that users can process packets

at line-rate.

The NetFPGA-SUME board is suitable for high-performance computing and high density

networking design. It is powered by Xilinx Virtex-7 690T and is co-developed by Digilent, Xilinx,

the University of Cambridge, and Stanford University. The board has been used in academic and

industrial researches including networks security, software defined networking, high-

performance network systems.

This getting started guide covers system requirements, infrastructure, hardware test, reference

designs and first reference switch project.

Summary of content (9 pages)

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Getting started with Digilent NetFPGA SUME, a Xilinx Virtex 7 FPGA board for high performance computing and networking systems Introduction The NetFPGA project is a group to develop open source hardware and software for rapid prototyping of high-speed, hardware-accelerated networking systems. The NetFPGA project is enabled by Field Programmable Gate Array (FPGA) technology so that users can process packets at line-rate.
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System Requirements 1. Operating Systems a. You can use any operating system that is supported by Xilinx Vivado Design Suite b. The NetFPGA team develops strictly on Linux, so the software components are developed for Linux. We recommend users to have Ubuntu 16.04. 2. CAD tools / IDE a. Xilinx Vivado Design Suite is required. The recommend version is Xilinx Vivado 2016.4. b. A valid license for Xilinx 10G MAC. 3. Network cables The NetFPGA-SUME board has four SFP+ connectors for 10G Ethernet.
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Infrastructure NetFPGA-SUME kit includes • NetFPGA-SUME board • A micro-USB cable • 4 unique MAC address stickers (one per 10G SFP+ Ethernet port) The NetFGPA support package has: • Reusable Verilog modules (IP Cores) • Verification Infrastructure o Simulate designs (from AXI interface) o Run tests against hardware o Test data generation libraries o Build using xSim and Scapy o Use Python scripts for stimuli construction and verification • Build Infrastructure o Bitstream generation using Xilinx tools o Re
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• • Utilities o Register I/O Software libraries Hardware test NetFPGA group has created a few hardware test so that the user can verify the hardware out of the box. Reference Designs The NetFPGA community offers a range of open source projects or reference designs. All can be directly downloaded from the git repository. To have access to reference designs, you must successfully register at http://netfpga.org/site/#/SUME_reg_form/.
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First Reference Switch Project Some useful reference designs include reference NIC, reference router, reference switch and reference switch lite. For example, NetSUME-FPGA will act as a learning switch if the reference switch project is loaded on the board. The incoming packets will be transmitted to the corresponding output ports, based on MAC address. Figure 1 shows the internal structure. Figure 1 The switching process can be broken down into five stages: 1. Input port (Rx Queues) 2.
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User can implement a Verilog module that makes the encryption and decryption of the payload. It was designed as a finite state machine (three states) to detect the header, which remains as it is, and the payload. This module was packaged as an IP and will be introduced in the switch pipeline. There are two ways to integrate the obtained IP into the main project. The block diagram (block design) is for someone who is familiar with Vivado block design.
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Now, user can run the simulation and debug the design. The simulation allows user to test the design without requiring lengthy synthesis process. Because the NetSUME-FPGA board has a complex FPGA architecture, the bitstream generation process takes more than 45 minutes. The simulation will be run in Vivado Simulator. To generate Ethernet packets, we used Scapy. The details is at https://github.com/NetFPGA/NetFPGA-SUME-public/wiki/NetFPGA-SUMESimulations .
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References: • NetFPGA Summer School courses: https://www.cl.cam.ac.uk/research/srg/netos/projects/netfpga/workshop/summerschool-2017/ • NetFPGA Wiki: https://github.