User Manual

Infrastructure
NetFPGA-SUME kit includes
NetFPGA-SUME board
A micro-USB cable
4 unique MAC address stickers (one per 10G SFP+ Ethernet port)
The NetFGPA support package has:
Reusable Verilog modules (IP Cores)
Verification Infrastructure
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Simulate designs (from AXI interface)
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Run tests against hardware
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Test data generation libraries
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Build using xSim and Scapy
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Use Python scripts for stimuli construction and verification
Build Infrastructure
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Bitstream generation using Xilinx tools
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Register system that generates addresses for all the registers and memories in a
project. Uses python and tcl scripts to generate HDL code and header files.