User Manual

User can implement a Verilog module that makes the encryption and decryption of the payload.
It was designed as a finite state machine (three states) to detect the header, which remains as it
is, and the payload. This module was packaged as an IP and will be introduced in the switch
pipeline. There are two ways to integrate the obtained IP into the main project. The block
diagram (block design) is for someone who is familiar with Vivado block design. The Tcl script is
good for version control or letting user understand Vivado GUI.
1. Use Vivado GUI and block diagram.
2. Use the Tcl scripts that were developed by NetFPGA community
After the encryption, Figure 2 shows the modified structure called Crypo-Switch.
Figure 2