Datasheet

JTAG-SMT2-NC™ Programming Module for Xilinx® FPGAs
Copyright Digilent, Inc. All rights reserved.
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Page 5 of 13
VIO
1149.7
Target
System
TDOC
TMSC
TDIC
TCKC
GND
VDD
VREF
TDO
JTAG-
SMT2-NC
GND
TMS
TDI
TCK
VIO
3.3V
VIO
200
VIO
1149.7
Target
System
TDOC
TMSC
TDIC
TCKC
GND
VDD
VREF
TDO
JTAG-
SMT2-NC
GND
TMS
TDI
TCK
VIO
3.3V
VIO
200
The Adept SDK provides an example application that demonstrates how to communicate with a Class T4 TAP
controller using the MScan, OScan0, and OScan1 scan formats.
3 GPIO Pins
The JTAG-SMT2-NC has three general purpose I/O pins that are useful for a variety of different applications (GPIO0,
GPIO1, and GPIO2). Each pin features high speed three-state input and output buffers. At power up, the JTAG-
SMT2-NC disables these output buffers and places the signals in a high-impedance state. Each signal remains in a
high-impedance state until a host application enables DPIO port 0 and configures the applicable pin as an output.
When the host application disables DPIO port 0, all GPIO pins revert to a high-impedance state. Weak pull-ups
(100K ohm) ensure that the GPIO signals do not float while not being actively driven (see Fig. 8).
IO Pin
(GPIO0, GPIO1, GPIO2)
100K
VREF
OEGPIOx
When customers use the JTAG-SMT2-NC to interface the scan chain of Xilinx’s Zynq platform, they should connect
the GPIO2 pin of the SMT2-NC to the Zynq’s PS_SRST_B pin. This connection allows the Xilinx Tools to reset the
Figure 6. Adding a current limiting resistor.
Figure 7. 200 Ohm resistor limiting current flow.
Figure 8. GPIO signals.