Datasheet

JTAG-SMT2-NC™ Programming Module for Xilinx® FPGAs
Copyright Digilent, Inc. All rights reserved.
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VCCO_0
VCCO_MIO1
PS_SRST_B
ZYNQ-
7000
TDO
TMS
TDI
TCK
GND
VDD
VREF
TDO
JTAG-
SMT2-NC
GND
TMS
TDI
TCK
GPIO0
GPIO1
GPIO2
VCCO_0
VCCO_MIO1
3.3V
VCCO_0
VCCO_MIO1
10K
Optional Reset
Button
Example 3: Interfacing a Zynq-7000 while retaining the Xilinx JTAG Header
Figure 11 below demonstrates how to connect the JTAG-SMT2-NC to Xilinx’s Zynq-7000 silicon alongside Xilinx’s
14-pin JTAG header. In this example, the open drain buffers allow both the SMT2-NC and Xilinx JTAG Header to
drive the PS_SRST_B pin, which may operate a different voltage than the Zynq’s JTAG pins.
Figure 10. Use of an open drain buffer.