Data Sheet

Arty FPGA Board Reference Manual
Copyright Digilent, Inc. All rights reserved.
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Page 18 of 18
The pins labeled V_P and V_N are connected to the VP_0 and VN_0 dedicated analog inputs of the FPGA. This pair
of pins can also be used as a differential analog input with voltage between 0-1V, but they cannot be used as
Digital I/O. The capacitor in the circuit shown in Figure 11.2.2 for this pair of pins is loaded on the Arty.
Figure 11.2.2. Dedicated analog inputs.
The XADC core within the Artix-7 is a dual channel 12-bit analog-to-digital converter capable of operating at 1
MSPS. Either channel can be driven by any of the analog inputs connected to the shield pins. The XADC core is
controlled and accessed from a user design via the Dynamic Reconfiguration Port (DRP). The DRP also provides
access to voltage monitors that are present on each of the FPGA’s power rails, and a temperature sensor that is
internal to the FPGA. For more information on using the XADC core, refer to the Xilinx document titled 7 Series
FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter. A demo that
uses the XADC core is available on the Arty resource center.