Data Sheet

Arty FPGA Board Reference Manual
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2 Designing with Arty
What makes Arty so flexible is its FPGA. Among their many features, FPGAs have the ability to transform into a
custom software-defined System-on-a-Chip (SoC). These “Soft SoC” FPGA configurations are designed graphically
using a tool called Vivado IP Integrator (Vivado IPI). In this tool, pre-built peripheral blocks are dragged from an
extensive library and dropped into your processing system as you see fit. These pre-built peripherals include
timers, UART/SPI/IIC controllers, and many of the other devices you would typically find in an SoC or
microcontroller. Ambitious users will also find that they can create their own peripheral blocks by writing them in a
Hardware Definition Language (HDL), specifically Verilog or VHDL. For those with no interest in learning HDL, the
Xilinx High Level Synthesis tool can be used to define custom peripheral blocks by writing them in C.
Arty's Soft SoC configurations are powered by MicroBlaze processor cores. MicroBlaze is a 32-bit RISC soft
processor core, designed specifically to be used in Xilinx FPGAs. The MicroBlaze processor in an Arty SoC
configuration is typically run at 100 MHz, though it is possible to design your SoC so that it can operate at over
200MHz. Arty supports large MicroBlaze programs with demanding memory requirements by providing 16MB of
non-volatile program memory and 256MB of DDR3L RAM.
Figure 2.1. Vivado IPI.
After you design your soft SoC configuration for Arty you can start writing programs for it. This is done by exporting
your SoC design out of Vivado IPI and into the Xilinx Software Development Kit (XSDK), an Integrated Development
Environment (IDE) for designing/debugging MicroBlaze programs in C. After the IPI to XSDK handoff, XSDK is
automatically configured to include libraries and examples for the peripheral blocks you've included in your SoC. At
this point, programming the Arty is very similar to programming other SoC or microcontroller platforms: Programs
are written in C, programmed into board over USB, and then optionally debugged in hardware. Soft SoC
configurations and MicroBlaze programs can also be loaded into the 16MB non-volatile program memory so that
they execute immediately after Arty is powered on.
Although the Arty is particularly well suited for MicroBlaze Soft SoC designs, it can also be programmed with a
Register-Transfer Level (RTL) circuit description like any other FPGA development platform. This design flow
requires that you describe your RTL circuit using an HDL within Vivado, and it does not use the Vivado IPI or XSDK
tools. Designing this way has many advantages, but is very unlike programming a single board computer, and