Datasheet

10
ADCS7476 , ADCS7477 , ADCS7478
SNAS192G –APRIL 2003–REVISED MAY 2016 www.ti.com
Product Folder Links: ADCS7476 ADCS7477 ADCS7478
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Timing Requirements (continued)
–40°C ≤ T
A
≤ 85°C, V
DD
= 2.7 V to 5.25 V, and f
SCLK
= 20 MHz (unless otherwise noted)
(1)
PARAMETER CONDITIONS MIN TYP MAX UNIT
(4) Measured with the load circuit (Figure 1), and defined as the time taken by the output to cross 1 V or 2 V.
(5) t
8
is derived from the time taken by the outputs to change by 0.5 V with the loading circuit (Figure 1). The measured number is then
adjusted to remove the effects of charging or discharging the 25-pF capacitor. This means t
8
is the true bus relinquish time, independent
of the bus loading.
t
4
Data access time after SCLK falling edge
(4)
V
DD
= 2.7 V to 3.6 V 40 ns
V
DD
= 4.75 V to 5.25 V 20 ns
t
5
SCLK low pulse width 0.4 × t
SCLK
ns
t
6
SCLK high pulse width 0.4 × t
SCLK
ns
t
7
SCLK to data valid hold time
V
DD
= 2.7 V to 3.6 V 7 ns
V
DD
= 4.75 V to 5.25 V 5 ns
t
8
SCLK falling edge to SDATA high
impedance
(5)
V
DD
= 2.7 V to 3.6 V 6 25 ns
V
DD
= 4.75 V to 5.25 V 5 25 ns
t
POWER-UP
Power-up time from full power down T
A
= 25°C 1 µs
Figure 1. Timing Test Circuit
Figure 2. ADCS7476 Serial Interface Timing Diagram