Datasheet

24
ADCS7476 , ADCS7477 , ADCS7478
SNAS192G –APRIL 2003–REVISED MAY 2016 www.ti.com
Product Folder Links: ADCS7476 ADCS7477 ADCS7478
Submit Documentation Feedback Copyright © 2003–2016, Texas Instruments Incorporated
Power Management (continued)
A plot of maximum power consumption versus throughput is shown in Figure 35. To calculate the power
consumption for a given throughput, remember that each time the part exits shutdown mode and enters normal
mode, one dummy conversion is required. Generally, the user puts the part into normal mode, execute one
dummy conversion followed by one valid conversion, and then put the part back into shutdown mode. When this
is done, the fraction of time spent in normal mode may be calculated by multiplying the throughput (in samples
per second) by 2 µs, the time taken to perform one dummy and one valid conversion. The power consumption
can then be found by multiplying the fraction of time spent in normal mode by the normal mode power
consumption figure. The power dissipated while the part is in shutdown mode is negligible.
For example, to calculate the power consumption at 300 kSPS with V
DD
= 5 V, begin by calculating the fraction of
time spent in normal mode: 300,000 samples/second x 2 µs = 0.6, or 60%. The power consumption at 300 kSPS
is then 60% of 17.5 mW (the maximum power consumption at V
DD
= 5 V) or 10.5 mW.
Figure 35. Maximum Power Consumption vs Throughput
10 Layout
10.1 Layout Guidelines
Capacitive coupling between noisy digital circuitry and sensitive analog circuitry can lead to poor performance.
The solution is to keep the analog and digital circuitry separated from each other and the clock line as short as
possible.
Digital circuits create substantial supply and ground current transients. This digital noise could have significant
impact upon system noise performance. To avoid performance degradation of the ADCS747x due to supply
noise, do not use the same supply for the ADCS747x that is used for digital logic.
Generally, analog and digital lines must cross each other at 90° to avoid crosstalk. However, to maximize
accuracy in high resolution systems, avoid crossing analog and digital lines altogether. It is important to keep
clock lines as short as possible and isolated from ALL other lines, including other digital lines. In addition, the
clock line must also be treated as a transmission line and be properly terminated.
The analog input must be isolated from noisy signal lines to avoid coupling of spurious signals into the input. Any
external component (that is, a filter capacitor) connected between the input pins and ground of the converter or
to the reference input pin and ground must be connected to a very clean point in the ground plane.
TI recommends the use of a single, uniform ground plane and the use of split power planes. The power planes
must be placed within the same board layer. All analog circuitry (input amplifiers, filters, reference components,
and so on) must be placed over the analog power plane. All digital circuitry and I/O lines must be placed over the
digital power plane. Furthermore, all components in the reference circuitry and the input signal chain that are
connected to ground must be connected together with short traces and enter the analog ground plane at a
single, quiet point.