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Digital Discovery Reference Manual

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The Digilent Digital Discovery™ is a combined logic analyzer and pattern generator instrument

that was created to be the ultimate embedded development companion. The Digital Discovery

was designed to optimize channels, speed, and portability. The small form factor facilitates easy

storage and provides a whole suite of advanced features to allow you to debug, visualize, and

simulate digital signals for most embedded projects. The digital inputs and outputs can be

connected to a circuit using simple wire probes or breadboard wires; alternatively, the Digital

Discovery High Speed Adapter and impedance-matched probes can be used to connect and

utilize the inputs and outputs for more advanced projects. The Digital Discovery is driven by the

free WaveForms software and can be configured to be any of the below instruments:



24-channel digital logic analyzer (1.2…3.3V CMOS, up to 800MS/s(with the High Speed

Adapter))



16-channel pattern generator (1.2…3.3V CMOS, 100MS/s)



16-channel virtual digital I/O including buttons, switches, and LEDs – perfect for logic

training applications



Two input/output digital trigger signals for linking multiple instruments (1.2…3.3V

CMOS)



A programmable power supply of 1.2…3.3V/100mA. The same voltage supplies the

Logic Analyzer input buffers and the Pattern Generator input/output buffers, for keeping

the logic level compatibility with the circuit under test.



Digital Bus Analyzers (SPI, I²C, UART, I2S, CAN, Parallel)

Summary of content (16 pages)

PAGE 1
Digital Discovery Reference Manual The Digilent Digital Discovery™ is a combined logic analyzer and pattern generator instrument that was created to be the ultimate embedded development companion. The Digital Discovery was designed to optimize channels, speed, and portability. The small form factor facilitates easy storage and provides a whole suite of advanced features to allow you to debug, visualize, and simulate digital signals for most embedded projects.
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The Digital Discovery was designed for anyone embarking on embedded development. Its features and specifications were deliberately chosen to maintain a small and portable form factor, withstand use in a variety of environments, and keep costs down, while balancing the requirements of operating on USB Power. 1.1 Architectural Overview and Block Diagram Digital Discovery's high-level block diagram is presented in Figure 2, below.
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In the sections that follow, schematics are not shown separately for identical blocks. For example, the Input Divider is only shown for DIN0 since the schematic for all other DIN1…DIN23 is identical. Figure 2. Digital Discovery Hardware block diagram. 2. I/O Level Translators Figure 3 shows the DIO user connectors and Figure 4 shows the I/O level translator for DIO24. DIO25 to DIO31 use similar discrete components, connected to pins 1A2…2A3, respectively 1B2…2B3 of IC2.
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Figure 4. I/O level translator. The LDO in Figure 5 generates the 4.3V to supply the level translator in Figure 4. The charge-pump in Figure 6 provides the the 6V reference for the clipper in Figure 7. When all ESD diodes protecting DIO_USR in Figure 3 are OFF, Q3B is OFF, and also Q4. If overvoltage is applied on some DIO_USR pins, rising VU5V2_ESD in Figure 7 above 5.2V, Q3B and Q4 turn ON , clipping VU5V2_ESD at approximately 5V. Figure 5. VCCIO_SW supply. Figure 6. VU6V0 supply.
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Figure Figure 7. Backpowering voltage clipper. 3. Input Dividers Figure 8 shows the DIN user connector and Figure 9 shows the Input Divider for DIN0. DIN1 to DIN23 use similar input circuitry. The Input Dividers block includes:  Frequency compensated voltage dividers: 10/11 resistive dividers with compensation for FPGA input capacitance. All the dividers together have the settable reference voltage VREFIO.
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Figure 8. DIN user connector. Figure 9. Input Divider. Figure 10 VREFIO reference. 4. Power supplies and control 4.1 Internal power supplies In Figure 11, IC16 limits the in-rush current when the device is connected to the USB port. INA214 is a current shunt amplifier, with a gain of 100. With Vref = 0.75V and R163 = 15mΩ, the output voltage is: VISNS_VBUS=100∙(VIN+−VIN−)+0.75V=1.5∙IVU5V0+0.
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The VBUS voltage is halved to VSNS_VBUS, for being also monitored. IC12 in Figure 11 is a triple power supply, generating the rails of 1.2V for the FPGA core, 1.5V for Bank 3 and DDR3 memory and 3.3V, for various circuits. Figure 11 VBUS monitoring. Figure 12. Internal voltage supplies. 4.2 Programmable power supply IC13 in Figure 13 generates the VCCIO_PROG, the variable voltage to supply the input and IO banks of the FPGA: VVCCIO_PROG=VFB∙(1+R144R146+R144R149)−VVSET_VCCIO∙R144R146=3.42V−VVSET_VCCIO∙0.
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IC14 is a window comparator: FAULT_USR is logical LOW, when VISNS_USR is either more than 1.5V (IVCCIO_USR>150mA) or less than 0.66V (IVCCIO_USR←18mA). If this happens, the FPGA turns EN_PWR_USR to LOW, which turns both Q1A and Q1B OFF, to protect VCCIO_USR against overcurrent and reverse current respectively. VCCIO_USR is halved to VSNS_USR, for being monitored. Figure 13. VCCIO_PROG supply. Figure 14. VCCIO_USR protection and switch. 4.3.
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Figure 15. ATtiny microcontroller. Figure 16. VSET_VCCIO setting DAC. Figure 17. VREF3V0 . 5. LEDs and DDR3 Memory Figure 18 shows the two tricolor LEDs used to symbolize the Digital discovery status. Figure 19 shows the DDR3 memory for the Logic Analyzer buffer.
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Figure 18. LEDs. Figure 19. DDR3 memory. 6. USB Controller The USB interface performs two tasks:   Programming the FPGA: There is no non-volatile FPGA configuration memory on the Digital Discovery. The WaveForms software identifies the connected device and downloads an appropriate .bit file at power-up, via a Digilent USB-JTAG interface. Adept run-time is used for low level protocols.
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7. FPGA The core of the Digital Discovery is the Xilinx Spartan6 FPGA circuit XC6SLX25.
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Figure 21. FPGA banks 0, 1 and 3. Figure 22 shows the voltage rails and decoupling for the FPGA. The internal core of the FPGA is supplied 1.2V. Banks 0 and 1 are supplied with the programmable VCCIO_PROG. By setting this from 1.2V to 3.3V, both inputs and IOs are set to be compatible with the I/O standard LVCMOS of the respective voltage. Notice that a protected version of VCCIO_PROG is also available to the user, as VCCIO_USR. This can be used to supply the Device/Circuit Under Test. Bank 3 is supplied 1.
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Figure 22. FPGA powering and decoupling. 8. Accessories The Digital Discovery package includes;  One 2×16 fly-wire assembly (datasheet), for the DIN_USR connector. 24DIN signals (various colors), 8 GND wires (black). The connector is keyed so that the correct pins are connected to the correct color wires. https://reference.digilentinc.com/_media/reference/instrumentation/digitaldiscovery/250-096_sn-1050323-1.pdf  One 2×6 fly-wire assembly (datasheet), for the DIO connectors.
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 One High Speed Adapter, for the DIN_USR connector. The High Speed Adapter is an alternative to the 2×16 fly-wire assembly. It provides access for 24 twisted cables. The adapter is not keyed, and both orientations can be used as the twisted wires are not color coded. However, if the adapter is plugged in with the ground arrows pointing down, the pins will be located as shown below:  High Speed Logic Probes (datasheet). Each twisted cable has a GND (black) wire twisted to a DIN_USR (colored) wire.
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9.2. Multi-purpose Digital I/O          16 digital I/Os arranged in two Pmod-style (2×6) connectors. Each of the 16 pins can be configured for input (Logic analyzer) or set as output 6). Algorithmic pattern generator (no buffers used) 7) Custom pattern buffer/ch.: 32Ksamples ROM Logic for implementing user defined Boolean functions and State Machines Bus Protocol Controllers (SPI, UART, I²C) 100MSps max. output sample rate (50MHz maximum output frequency).
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3) , 8) , 9) The FPGA DIN and DIO pins are set to LVCMOS18_JEDEC IOSTANDARD. The supply voltage of the associated FPGA banks is set (by user) to any value from 1.2V to 3.3V. The threshold level (at the FPGA pins) is about 45% of the bank supply voltage. For standard voltages of: 1.2V, 1.5V, 1.8V, 2.5V, 3.3V, the threshold levels (at the FPGA pins) are: 0.58V, 0.7V, 0.82V, 1.1V and 1.42V respectively. 4) 10) , Setting the voltage to 3.3V, 5V logic inputs are tolerated but the input threshold is 1.42V.