User manual

3)
,
8)
,
9)
The FPGA DIN and DIO pins are set to LVCMOS18_JEDEC IOSTANDARD. The supply
voltage of the associated FPGA banks is set (by user) to any value from 1.2V to 3.3V. The
threshold level (at the FPGA pins) is about 45% of the bank supply voltage. For standard
voltages of: 1.2V, 1.5V, 1.8V, 2.5V, 3.3V, the threshold levels (at the FPGA pins) are: 0.58V,
0.7V, 0.82V, 1.1V and 1.42V respectively.
4)
,
10)
Setting the voltage to 3.3V, 5V logic inputs are tolerated but the input threshold is 1.42V.
LVCMOS 3.3V output signals are compatible to most external logical circuits supplied with 5V.
5)
Trigger Detectors and Trigger Distribution Networks are implemented in the FPGA. This allows
real time triggering and cross-triggering of different instruments within the Digital Discovery
device. Using external Trigger inputs/outputs, cross-triggering between multiple Digital
Discovery devices is possible.
7)
Real time implemented in the FPGA configuration.
https://reference.digilentinc.com/reference/instrumentation/digital-discovery/reference-ma... 3/14/2017