User manual

The Digital Discovery was designed for anyone embarking on embedded development. Its
features and specifications were deliberately chosen to maintain a small and portable form factor,
withstand use in a variety of environments, and keep costs down, while balancing the
requirements of operating on USB Power.
1.1 Architectural Overview and Block Diagram
Digital Discovery's high-level block diagram is presented in Figure 2, below. The core of the
Digital Discovery 2 is the Xilinx® Spartan®-6 FPGA (specifically, the XC6SLX25-2 device).
The WaveForms application automatically programs the Discovery’s FPGA at start-up with a
configuration file designed to implement a multi-function test and measurement instrument.
Once programmed, the FPGA inside the Discovery communicates with the PC-based
WaveForms application via a USB 2.0 connection. The WaveForms software works with the
FPGA to control all the functional blocks of the Digital Discovery, including setting parameters,
acquiring data, and transferring and storing data into the DDR3 memory. Signals and equations
also use certain naming conventions. Signals in the Input block use “DIN” prefix to indicate
these are inputs only. Signals in the Input/Output block use “DIO” prefix. Signals at the user
connectors include “USR” in their names, while signals at the FPGA pins include “FPGA”.
Signals at the FPGA pins driving the pull resistors for DIO signals, include “PULL” in their
names. DIN inputs are indexed 0 to 23, DIO input/outputs are indexed 24 to 39. Memory signals
have the “DDR” prefix. Supply rails show the voltage with the VCC prefix. Referring to the
block diagram in Figure 2 below:
 The I/O Level Translators build the bidirectional interface for input/output pins (used in
the Pattern Generator, Static IO, and Logic Analyzer)
 The Input Dividers are the conditioning circuits for the input pins (used in the Logic
Analyzer)
 The FPGA banks are supplied at different voltages:
o Bank 0, Bank1: VCCIO_PROG, a variable voltage, settable in the range
1.2V…3.3V. The logic standard is set to: LVCMOS18_JEDEC. The threshold
voltage is about 0.45*VCCIO_PROG.
o Bank 2: VCC3V3, a fixed voltage of 3.3V.
o Bank 3: VCC1V5, a fixed voltage of 1.5V.
 A replica of VCCIO_PROG is also available to the user, as VCCIO_USR, under the V
user switch control.
 The DDR3 Data Memory block stores the Logic analyzer acquired data.
 The Power Supplies and Control block generates all internal supply voltages as well as
user supply programmable voltage. The control block also monitors the device power
consumption for USB compliance.
 The USB Controller interfaces with the PC for programming the volatile FPGA memory
after power on or when a new configuration is requested. After that, it performs the data
transfer between the PC and FPGA.
 The Calibration Memory stores all calibration parameters. The Digital Discovery
includes no analog calibration circuitry. Instead, a calibration operation is performed at
manufacturing (or by the user), and parameters are stored in memory. The WaveForms
software uses these parameters to adjust the acquired data and the generated signals.