User manual

In the sections that follow, schematics are not shown separately for identical blocks. For
example, the Input Divider is only shown for DIN0 since the schematic for all other
DIN1…DIN23 is identical.
Figure 2. Digital Discovery Hardware block diagram.
2. I/O Level Translators
Figure 3 shows the DIO user connectors and Figure 4 shows the I/O level translator for DIO24.
DIO25 to DIO31 use similar discrete components, connected to pins 1A2…2A3, respectively
1B2…2B3 of IC2.
The I/O Level Translators block includes: - Input protection: series PTC (33Ω, positive thermal
coefficient thermistor) and parallel ESD/overvoltage diodes to 5.2V and GND. - Voltage level
translators, SN74CBT3384C. When DIO_USR signals are driven by the DUT, the voltage at the
FPGA pins is limited at VCCIO_SW-1V = 3.3V. When the FPGA drives DIO_USR signals, they
pass unlimited trough the low impedance SN74CBT3384C buffer. - Pull resistors: 10k,
individually settable as Pull-Up, Pull-Down or High-Z. This is done with a second FPGA pin
associated to each DIO, which can be driven High, Low or HiZ. The Pull-Up voltage is
VCCIO_PROG. - DIO_FPGA pin: the bank supply voltage is VCCIO_PROG> The WaveForms
software can set VCCIO_PROG from 1.2 to 3.3V. The FPGA input threshold level is about 45%
of VCCIO_PROG. The output strength can be set from 2mA to 16mA. The output slew rate can
be set as: Quiet, Slow or Fast.
Figure 3. DIO user connectors.