User manual

Figure Figure 7. Backpowering voltage clipper.
3. Input Dividers
Figure 8 shows the DIN user connector and Figure 9 shows the Input Divider for DIN0. DIN1 to
DIN23 use similar input circuitry.
The Input Dividers block includes:
 Frequency compensated voltage dividers: 10/11 resistive dividers with compensation for
FPGA input capacitance. All the dividers together have the settable reference voltage
VREFIO. Setting VREFIO close to the logical threshold voltage provides the highest
sensitivity, while setting VREFIO at GND or logical supply voltage increase the noise
immunity. The voltage at the FPGA pin:
V DIN_FPGA =1011∙V DIN_USR +111∙V REFIO (1)
 The reference voltage VREFIO is generated as in Figure 10. DIN_VREF_H and
DIN_VREF_L are connected to FPGA pins in bank 1. Bank1 is supplied at VCCIO.
VREFIO can be set at:
o 0V, when DIN_VREF_H = DIN_VREF_L = low
o 0.43*VCCIO_PROG, when DIN_VREF_H = high, DIN_VREF_L = low
o VCCIO_PROG, when DIN_VREF_H = DIN_VREF_L = high.
 ESD/Overvoltage protection: Shottky diodes to VCC3V3.
 DIN_FPGA pin: the bank supply voltage is VCCIO_PROG. The WaveForms software
can set VCCIO_PROG from 1.2 to 3.3V. The FPGA input threshold level is about 45%
of VCCIO_PROG.