Datasheet

ManualsBrandsDIGILENT ManualsDev Kits410-340

Micron Serial NOR Flash Memory

3V, Multiple I/O, 4KB Sector Erase

N25Q256A

Features

• SPI-compatible serial bus interface

• Double transfer rate (DTR) mode

• 2.7–3.6V single supply voltage

• 108 MHz (MAX) clock frequency supported for all

protocols in single transfer rate (STR) mode

• 54 MHz (MAX) clock frequency supported for all

protocols in DTR mode

• Dual/quad I/O instruction provides increased

throughput up to 54 MB/s

• Supported protocols

– Extended SPI, dual I/O, and quad I/O

– DTR mode supported on all

• Execute-in-place (XIP) mode for all three protocols

– Configurable via volatile or nonvolatile registers

– Enables memory to work in XIP mode directly af-

ter power-on

• PROGRAM/ERASE SUSPEND operations

• Continuous read of entire memory via a single com-

mand

– Fast read

– Quad or dual output fast read

– Quad or dual I/O fast read

• Flexible to fit application

– Configurable number of dummy cycles

– Output buffer configurable

• Software reset

• 3-byte and 4-byte addressability mode supported

• 64-byte, user-lockable, one-time programmable

(OTP) dedicated area

• An additional reset pin is available on the following

devices

– N25Q256A83ESF40x, N25Q256A83E1240x,

N25Q256A83ESFA0F

• Erase capability

– Subsector erase 4KB uniform granularity blocks

– Sector erase 64KB uniform granularity blocks

– Full-chip erase

• Write protection

– Software write protection applicable to every

64KB sector via volatile lock bit

– Hardware write protection: protected area size

defined by five nonvolatile bits (BP0, BP1, BP2,

BP3, and TB)

– Additional smart protections, available upon re-

quest

• Electronic signature

– JEDEC-standard 2-byte signature (BA19h)

– Unique ID of 17 read-only bytes including: addi-

tional extended device ID (EDID) to identify de-

vice factory options; customized factory data

• Minimum 100,000 ERASE cycles per sector

• More than 20 years data retention

• Packages JEDEC standard, all RoHS compliant

– V-PDFN-8/8mm x 6mm (also known as SON,

DFPN, MLP, MLF)

– SOP2-16/300mils (also known as SO16W, SO16-

Wide, SOIC-16)

– T-PBGA-24b05/6mm x 8mm (also known as

TBGA24)

3V, 256Mb: Multiple I/O Serial Flash Memory

Features

09005aef84566603

n25q_256mb_65nm.pdf - Rev. W 11/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

Summary of content (91 pages)

PAGE 1
3V, 256Mb: Multiple I/O Serial Flash Memory Features Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q256A Features • • • • • • • • • • • • • • • • • Write protection – Software write protection applicable to every 64KB sector via volatile lock bit – Hardware write protection: protected area size defined by five nonvolatile bits (BP0, BP1, BP2, BP3, and TB) – Additional smart protections, available upon request • Electronic signature – JEDEC-standard 2-byte signature (BA19h) – Uniq
PAGE 2
3V, 256Mb: Multiple I/O Serial Flash Memory Features Contents Device Description ........................................................................................................................................... 6 Features ....................................................................................................................................................... 6 3-Byte Address and 4-Byte Address Modes .....................................................................................
PAGE 3
V, 256Mb: Multiple I/O Serial Flash Memory Features PROGRAM/ERASE SUSPEND Command ..................................................................................................... PROGRAM/ERASE RESUME Command ...................................................................................................... RESET Operations .......................................................................................................................................... RESET ENABLE and RESET MEMORY Command .
PAGE 4
3V, 256Mb: Multiple I/O Serial Flash Memory Features List of Figures Figure 1: Logic Diagram ................................................................................................................................... 7 Figure 2: 8-Lead, VDFPN8 – MLP8 (Top View) .................................................................................................. 8 Figure 3: 16-Lead, Plastic Small Outline – SO16 (Top View) ...............................................................................
PAGE 5
3V, 256Mb: Multiple I/O Serial Flash Memory Features List of Tables Table 1: Signal Descriptions ........................................................................................................................... Table 2: Sectors[511:0] ................................................................................................................................... Table 3: Data Protection using Device Protocols ......................................................................................
PAGE 6
3V, 256Mb: Multiple I/O Serial Flash Memory Device Description Device Description The N25Q is the first high-performance multiple input/output serial Flash memory device manufactured on 65nm NOR technology. It features execute-in-place (XIP) functionality, advanced write protection mechanisms, and a high-speed SPI-compatible bus interface. The innovative, high-performance, dual and quad input/output instructions enable double or quadruple the transfer bandwidth for READ and PROGRAM operations.
PAGE 7
3V, 256Mb: Multiple I/O Serial Flash Memory Device Description All protocols support XIP operation. For flexibility, multiple XIP entry and exit methods are available. For applications that must enter XIP mode immediately after powering up, XIP mode can be set as the default mode through the nonvolatile configuration register bits. Device Configurability The N25Q family offers additional features that are configured through the nonvolatile configuration register for default and/or nonvolatile settings.
PAGE 8
3V, 256Mb: Multiple I/O Serial Flash Memory Signal Assignments Signal Assignments Figure 2: 8-Lead, VDFPN8 – MLP8 (Top View) Notes: S# 1 8 VCC DQ1 2 7 HOLD#/DQ3 W#/VPP/DQ2 3 6 C VSS 4 5 DQ0 1. On the underside of the MLP8 package, there is an exposed central pad that is pulled internally to VSS and must not be connected to any other voltage or signal line on the PCB. 2. Reset functionality is available in devices with a dedicated part number.
PAGE 9
3V, 256Mb: Multiple I/O Serial Flash Memory Signal Assignments Figure 4: 24-Ball TBGA (Balls Down) 1 2 3 4 5 NC NC RESET/NC NC NC C VSS VCC NC NC S# NC W#/VPP/DQ2 NC NC DQ1 DQ0 HOLD#/DQ3 NC NC NC A B C D E Notes: 09005aef84566603 n25q_256mb_65nm.pdf - Rev. W 11/16 EN NC NC NC 1. See Part Number Ordering Information for complete package names and details. 2. Ball A4 is NC, except for the N25Q256A83E1240x device, where it is used as RESET. 9 Micron Technology, Inc.
PAGE 10
3V, 256Mb: Multiple I/O Serial Flash Memory Signal Descriptions Signal Descriptions The signal description table below is a comprehensive list of signals for the N25 family devices. All signals listed may not be supported on this device. See Signal Assignments for information specific to this device. Table 1: Signal Descriptions Symbol Type Description C Input Clock: Provides the timing of the serial interface.
PAGE 11
3V, 256Mb: Multiple I/O Serial Flash Memory Signal Descriptions Table 1: Signal Descriptions (Continued) Symbol Type HOLD# Control Input HOLD: Pauses any serial communications with the device without deselecting the device. DQ1 (output) is High-Z. DQ0 (input) and the clock are "Don't Care." To enable HOLD, the device must be selected with S# driven LOW.
PAGE 12
3V, 256Mb: Multiple I/O Serial Flash Memory Memory Organization Memory Organization Memory Configuration and Block Diagram Each page of memory can be individually programmed. Bits are programmed from one through zero. The device is subsector, sector, or bulk-erasable, but not page-erasable. Bits are erased from zero through one.
PAGE 13
3V, 256Mb: Multiple I/O Serial Flash Memory Memory Map – 256Mb Density Memory Map – 256Mb Density Table 2: Sectors[511:0] Address Range Sector Subsector Start End 511 8191 01FF F000h 01FF FFFFh ⋮ ⋮ ⋮ 8176 01FF 0000h 01FF 0FFFh ⋮ ⋮ ⋮ ⋮ 255 4095 00FF F000h 00FF FFFFh ⋮ ⋮ ⋮ 4080 00FF 0000h 00FF 0FFFh ⋮ ⋮ ⋮ ⋮ 127 2047 007F F000h 007F FFFFh ⋮ ⋮ ⋮ 2032 007F 0000h 007F 0FFFh ⋮ ⋮ ⋮ ⋮ 63 1023 003F F000h 003F FFFFh ⋮ ⋮ ⋮ 1008 003F 0000h 003F 0FFFh ⋮ ⋮ ⋮ ⋮ 0
PAGE 14
3V, 256Mb: Multiple I/O Serial Flash Memory Device Protection Device Protection Table 3: Data Protection using Device Protocols Note 1 applies to the entire table Protection by: Description Power-on reset and internal timer Protects the device against inadvertent data changes while the power supply is outside the operating specification.
PAGE 15
3V, 256Mb: Multiple I/O Serial Flash Memory Device Protection Block Protection Areas Table 5: Protected Area Sizes – Upper Area Note 1 applies to the entire table Status Register Content Memory Content Top/ Bottom Bit BP3 BP2 BP1 BP0 Protected Area Unprotected Area 0 0 0 0 0 None All sectors 0 0 0 0 1 Sector 511 Sectors (0 to 510) 0 0 0 1 0 Sectors (510 to 511) Sectors (0 to 509) 0 0 0 1 1 Sectors (508 to 511) Sectors (0 to 507) 0 0 1 0 0 Sectors (504 to 511) Secto
PAGE 16
3V, 256Mb: Multiple I/O Serial Flash Memory Device Protection Table 6: Protected Area Sizes – Lower Area (Continued) Note 1 applies to the entire table Status Register Content Memory Content Top/ Bottom Bit BP3 BP2 BP1 BP0 Protected Area Unprotected Area 1 1 0 0 1 Sectors (0 to 255) Sectors (256 to 511) 1 1 0 1 0 All sectors None 1 1 0 1 1 All sectors None 1 1 1 0 0 All sectors None 1 1 1 0 1 All sectors None 1 1 1 1 0 All sectors None 1 1 1 1 1 All se
PAGE 17
3V, 256Mb: Multiple I/O Serial Flash Memory Serial Peripheral Interface Modes Serial Peripheral Interface Modes The device can be driven by a microcontroller while its serial peripheral interface is in either of the two modes shown here. The difference between the two modes is the clock polarity when the bus master is in standby mode and not transferring data. Input data is latched in on the rising edge of the clock, and output data is available from the falling edge of the clock.
PAGE 18
3V, 256Mb: Multiple I/O Serial Flash Memory Serial Peripheral Interface Modes Figure 6: Bus Master and Memory Devices on the SPI Bus VSS VCC R SDO SPI interface: (CPOL, CPHA) = (0, 0) or (1, 1) SDI SCK VCC C SPI bus master DQ1 DQ0 R CS3 SPI memory device VCC C VSS R DQ1 DQ0 SPI memory device VCC C VSS R DQ1 DQ0 VSS SPI memory device CS2 CS1 S# W# HOLD# S# W# HOLD# S# W# HOLD# Figure 7: SPI Modes CPOL CPHA 0 0 C 1 1 C DQ0 MSB DQ1 09005aef84566603 n25q_256mb_65nm.pdf - Rev.
PAGE 19
3V, 256Mb: Multiple I/O Serial Flash Memory SPI Protocols SPI Protocols Table 8: Extended, Dual, and Quad SPI Protocols Protocol Name Command Input Extended DQ0 Multiple DQn lines, depending on the command Dual DQ[1:0] DQ[1:0] Address Input Data Input/Output Description Multiple DQn Device default protocol from the factory. Additional comlines, depending mands extend the standard SPI protocol and enable address on the command or data transmission on multiple DQn lines.
PAGE 20
3V, 256Mb: Multiple I/O Serial Flash Memory Nonvolatile and Volatile Registers Nonvolatile and Volatile Registers The device features the following volatile and nonvolatile registers that users can access to store device parameters and operating configurations: • • • • • • Status register Nonvolatile and volatile configuration registers Extended address register Enhanced volatile configuration register Flag status register Lock register Note: The lock register is defined in READ LOCK REGISTER Command.
PAGE 21
3V, 256Mb: Multiple I/O Serial Flash Memory Nonvolatile and Volatile Registers Status Register Table 9: Status Register Bit Definitions Note 1 applies to entire table Bit Name Settings Description Notes 7 Status register 0 = Enabled write enable/disable 1 = Disabled Nonvolatile bit: Used with the W/VPP signal to enable or disable writing to the status register.
PAGE 22
3V, 256Mb: Multiple I/O Serial Flash Memory Nonvolatile and Volatile Registers Table 10: Nonvolatile Configuration Register Bit Definitions Note 1 applies to entire table Bit Name Settings Description Notes 15:12 Number of dummy clock cycles 0000 (identical to 1111) 0001 0010 . . 1101 1110 1111 Sets the number of dummy clock cycles subsequent to all FAST READ commands. The default setting targets the maximum allowed frequency and guarantees backward compatibility.
PAGE 23
3V, 256Mb: Multiple I/O Serial Flash Memory Nonvolatile and Volatile Registers 3. If the number of dummy clock cycles is insufficient for the operating frequency, the memory reads wrong data. The number of cycles must be set according to and sufficient for the clock frequency, which varies by the type of FAST READ command, as shown in the Supported Clock Frequencies table. 4. If bits 2 and 3 are both set to 0, the device operates in quad I/O.
PAGE 24
3V, 256Mb: Multiple I/O Serial Flash Memory Nonvolatile and Volatile Registers Table 12: Sequence of Bytes During Wrap Starting Address 16-Byte Wrap 32-Byte Wrap 64-Byte Wrap 0 0-1-2- . . . -15-0-1- . . 0-1-2- . . . -31-0-1- . . 0-1-2- . . . -63-0-1- . . 1 1-2- . . . -15-0-1-2- . . 1-2- . . . -31-0-1-2- . . 1-2- . . . -63-0-1-2- . . 15 15-0-1-2-3- . . . -15-0-1- . . 15-16-17- . . . -31-0-1- . . 15-16-17- . . . -63-0-1- . . 31 31-16-17- . . . -31-16-17- . . 31-0-1-2-3- . . . -31-0-1- . .
PAGE 25
3V, 256Mb: Multiple I/O Serial Flash Memory Nonvolatile and Volatile Registers Extended Address Register For devices whose A[MAX:MIN] equals A[23:0], the N25 family includes an extended address register that provides a fourth address byte A[31:24], enabling access to memory beyond 128Mb. Extended address register bit 0 is used to select the upper 128Mb segment or the lower 128Mb segment of the memory array.
PAGE 26
3V, 256Mb: Multiple I/O Serial Flash Memory Nonvolatile and Volatile Registers 128Mb segmentation selection. If 4-byte addressing is enabled, extended address register settings are ignored. Enhanced Volatile Configuration Register Table 16: Enhanced Volatile Configuration Register Bit Definitions Note 1 applies to entire table Bit Name Settings Description Notes 7 Quad I/O protocol 0 = Enabled Enables or disables quad I/O protocol.
PAGE 27
3V, 256Mb: Multiple I/O Serial Flash Memory Nonvolatile and Volatile Registers Table 17: Flag Status Register Bit Definitions (Continued) Note 1 applies to entire table Bit Name Settings Description Notes 6 Erase suspend 0 = Not in effect 1 = In effect Status bit: Indicates whether an ERASE operation has been or is going to be suspended. 5 Erase 0 = Clear 1 = Failure or protection error Error bit: Indicates whether an ERASE operation has succeeded or failed.
PAGE 28
3V, 256Mb: Multiple I/O Serial Flash Memory Command Definitions Command Definitions Table 18: Command Set Note 1 applies to entire table Code Extended Dual I/O Quad I/O Data Bytes Notes RESET ENABLE 66h Yes Yes Yes 0 2 RESET MEMORY 99h Command RESET Operations IDENTIFICATION Operations READ ID 9E/9Fh Yes No No 1 to 20 2 MULTIPLE I/O READ ID AFh No Yes Yes 1 to 3 2 READ SERIAL FLASH DISCOVERY PARAMETER 5Ah Yes Yes Yes 1 to ∞ 3 READ 03h Yes No No 1 to ∞ 4 FAST READ
PAGE 29
3V, 256Mb: Multiple I/O Serial Flash Memory Command Definitions Table 18: Command Set (Continued) Note 1 applies to entire table Code Extended Dual I/O Quad I/O Data Bytes Notes WRITE ENABLE 06h Yes Yes Yes 0 2 WRITE DISABLE 04h Yes Yes Yes 1 to ∞ 2 1 2, 13 Command REGISTER Operations READ STATUS REGISTER 05h WRITE STATUS REGISTER 01h READ LOCK REGISTER E8h WRITE LOCK REGISTER E5h READ FLAG STATUS REGISTER 70h CLEAR FLAG STATUS REGISTER 50h READ NONVOLATILE CONFIGURATION RE
PAGE 30
3V, 256Mb: Multiple I/O Serial Flash Memory Command Definitions Table 18: Command Set (Continued) Note 1 applies to entire table Code Extended Dual I/O Quad I/O Data Bytes Notes SECTOR ERASE D8h Yes Yes Yes 0 4, 13 4-BYTE SECTOR ERASE DCh Command 4, 13, 14 BULK ERASE C7h Yes Yes Yes 0 4, 13 PROGRAM/ERASE RESUME 7Ah Yes Yes Yes 0 2, 13 PROGRAM/ERASE SUSPEND 75h Yes Yes Yes 1 to 64 ONE-TIME PROGRAMMABLE (OTP) Operations READ OTP ARRAY 4Bh PROGRAM OTP ARRAY 42h 5 4, 13
PAGE 31
3V, 256Mb: Multiple I/O Serial Flash Memory Command Definitions 15. The code 38h is valid only for part numbers N25Q256A83ESF40x, N25Q256A83E1240x, and N25Q256A83ESFA0F; the code 12h is valid for the other part numbers. 16. The WRITE ENABLE command must be issued first before this command can be executed. Not necessary for part numbers N25Q256A83ESF40x, N25Q256A83E1240x, and N25Q256A83ESFA0F. 09005aef84566603 n25q_256mb_65nm.pdf - Rev. W 11/16 EN 31 Micron Technology, Inc.
PAGE 32
3V, 256Mb: Multiple I/O Serial Flash Memory READ REGISTER and WRITE REGISTER Operations READ REGISTER and WRITE REGISTER Operations READ STATUS REGISTER or FLAG STATUS REGISTER Command To initiate a READ STATUS REGISTER command, S# is driven LOW. For extended SPI protocol, the command code is input on DQ0, and output on DQ1. For dual SPI protocol, the command code is input on DQ[1:0], and output on DQ[1:0]. For quad SPI protocol, the command code is input on DQ[3:0], and is output on DQ[3:0].
PAGE 33
3V, 256Mb: Multiple I/O Serial Flash Memory READ REGISTER and WRITE REGISTER Operations on DQ[3:0]. The operation is terminated by driving S# HIGH at any time during data output. The nonvolatile configuration register can be read continuously. After all 16 bits of the register have been read, a 0 is output. All reserved fields output a value of 1.
PAGE 34
3V, 256Mb: Multiple I/O Serial Flash Memory READ REGISTER and WRITE REGISTER Operations Figure 11: WRITE REGISTER Command Extended 0 7 8 9 10 11 12 13 15 14 C LSB LSB DIN Command DQ0 MSB Dual DIN DIN DIN DIN DIN DIN DIN MSB 0 3 4 5 6 7 C LSB MSB Quad LSB DIN Command DQ[1:0] DIN DIN DIN DIN MSB 0 1 2 3 C LSB LSB Command DQ[3:0] MSB Notes: DIN DIN DIN MSB 1. Supports all WRITE REGISTER commands except WRITE LOCK REGISTER. 2.
PAGE 35
3V, 256Mb: Multiple I/O Serial Flash Memory READ REGISTER and WRITE REGISTER Operations Because register bits are volatile, change to the bits is immediate. If S# is not driven HIGH, the command is not executed, flag status register error bits are not set, and the write enable latch remains set to 1. Reserved bits are not affected by this command.
PAGE 36
3V, 256Mb: Multiple I/O Serial Flash Memory READ REGISTER and WRITE REGISTER Operations Table 19: Lock Register (Continued) Note 1 applies to entire table Bit Name 0 Settings Sector write lock Note: Description 0 = Cleared (Default) Volatile bit: the device always powers-up with this bit cleared, 1 = Set which means that PROGRAM and ERASE operations in this sector can be executed and sector content modified. When this bit is set, PROGRAM and ERASE operations in this sector will not be executed. 1.
PAGE 37
3V, 256Mb: Multiple I/O Serial Flash Memory READ REGISTER and WRITE REGISTER Operations fect. If S# is not driven HIGH, the command is not executed, flag status register error bits are not set, and the write enable latch remains set to 1.
PAGE 38
3V, 256Mb: Multiple I/O Serial Flash Memory READ IDENTIFICATION Operations READ IDENTIFICATION Operations READ ID and MULTIPLE I/O READ ID Commands To execute the READ ID or MULTIPLE I/O READ ID commands, S# is driven LOW and the command code is input on DQn. The device outputs the information shown in the tables below. If an ERASE or PROGRAM cycle is in progress when the command is executed, the command is not decoded and the command cycle in progress is not affected.
PAGE 39
3V, 256Mb: Multiple I/O Serial Flash Memory READ IDENTIFICATION Operations Figure 14: READ ID and MULTIPLE I/O Read ID Commands Extended (READ ID) 0 7 16 15 8 31 32 C LSB DQ0 Command MSB LSB DOUT DOUT High-Z DQ1 MSB DOUT 0 3 UID Device identification 8 7 4 LSB DOUT DOUT MSB MSB Manufacturer identification Dual (MULTIPLE I/O READ ID ) LSB DOUT 15 C LSB DQ[1:0] LSB DOUT DOUT Command MSB MSB DOUT MSB Manufacturer identification Quad (MULTIPLE I/O READ ID ) 0 LSB DOUT 1 Dev
PAGE 40
3V, 256Mb: Multiple I/O Serial Flash Memory READ IDENTIFICATION Operations Table 23: Serial Flash Discovery Parameter Data Structure Compliant with JEDEC standard JC-42.4 1775.
PAGE 41
3V, 256Mb: Multiple I/O Serial Flash Memory READ IDENTIFICATION Operations Table 24: Parameter ID Compliant with JEDEC standard JC-42.4 1775.
PAGE 42
3V, 256Mb: Multiple I/O Serial Flash Memory READ IDENTIFICATION Operations Table 24: Parameter ID (Continued) Compliant with JEDEC standard JC-42.4 1775.
PAGE 43
3V, 256Mb: Multiple I/O Serial Flash Memory READ MEMORY Operations READ MEMORY Operations The device supports default reading and writing to an A[MAX:MIN] of A[23:0] (3-byte address). Reading and writing to an A[MAX:MIN] of A[31:0] (4-byte address) is also supported. Selection of the 3-byte or 4-byte address range can be enabled in two ways: setting the nonvolatile configuration register or entering the ENABLE 4-BYTE ADDRESS MODE or EXIT 4-BYTE ADDRESS MODE commands.
PAGE 44
3V, 256Mb: Multiple I/O Serial Flash Memory READ MEMORY Operations Table 25: Command/Address/Data Lines for READ MEMORY Commands (Continued) Note 1 applies to entire table Command Name DUAL QUAD DUAL OUTPUT INPUT/OUTPUT QUAD OUTPUT INPUT/OUTPUT FAST READ FAST READ FAST READ FAST READ READ FAST READ STR Mode 03h 0Bh 3Bh BBh DTR Mode – 0Dh 3Dh BDh 6Dh EDh Data Output – DQ[3:0] – – DQ[3:0] DQ[3:0] Notes: 09005aef84566603 n25q_256mb_65nm.pdf - Rev. W 11/16 EN 6Bh EBh 1.
PAGE 45
3V, 256Mb: Multiple I/O Serial Flash Memory READ MEMORY Operations 4-Byte Address To execute 4-byte READ MEMORY commands, S# is driven LOW. The command code is input on DQn, followed by input on DQn of four address bytes. Each address bit is latched in during the rising edge of the clock. The addressed byte can be at any location, and the address automatically increments to the next address after each byte of data is shifted out; therefore, the entire memory can be read with a single command.
PAGE 46
3V, 256Mb: Multiple I/O Serial Flash Memory READ MEMORY Operations Figure 15: READ Command Extended 0 7 8 Cx C LSB A[MIN] Command DQ[0] MSB A[MAX] DOUT High-Z DQ1 DOUT DOUT DOUT DOUT DOUT DOUT LSB DOUT DOUT MSB Don’t Care Note: 1. Cx = 7 + (A[MAX] + 1).
PAGE 47
3V, 256Mb: Multiple I/O Serial Flash Memory READ MEMORY Operations Figure 17: DUAL OUTPUT FAST READ Command – STR Extended 0 7 8 Cx C LSB MSB DOUT DOUT DOUT LSB DOUT DOUT DOUT DOUT DOUT DOUT DOUT LSB DOUT DOUT A[MIN] Command DQ0 A[MAX] High-Z DQ1 DOUT MSB Dummy cycles Dual 0 3 4 Cx C LSB A[MIN] DOUT Command DQ[1:0] MSB A[MAX] DOUT MSB Dummy cycles Notes: 1. Cx = 7 + (A[MAX] + 1). 2. Shown here is the DUAL OUTPUT FAST READ timing for the extended SPI protocol.
PAGE 48
3V, 256Mb: Multiple I/O Serial Flash Memory READ MEMORY Operations Figure 19: QUAD OUTPUT FAST READ Command – STR Extended 0 7 8 Cx C LSB A[MIN] Command DQ0 MSB DOUT LSB DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT A[MAX] High-Z DQ[2:1] ‘1’ DQ3 MSB Dummy cycles Quad 0 1 2 Cx C LSB A[MIN] DOUT Command DQ[3:0] MSB A[MAX] LSB DOUT DOUT MSB Dummy cycles Notes: 1. Cx = 7 + (A[MAX] + 1). 2. Shown here is the QUAD OUTPUT FAST READ timing for the extended SPI protocol.
PAGE 49
3V, 256Mb: Multiple I/O Serial Flash Memory READ MEMORY Operations 2. Shown here is the QUAD INPUT/OUTPUT FAST READ timing for the extended SPI protocol. The quad timing shown for the FAST READ command is the equivalent of the QUAD INPUT/OUTPUT FAST READ timing for the quad SPI protocol. 09005aef84566603 n25q_256mb_65nm.pdf - Rev. W 11/16 EN 49 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2011 Micron Technology, Inc. All rights reserved.
PAGE 50
3V, 256Mb: Multiple I/O Serial Flash Memory READ MEMORY Operations READ MEMORY Operations Timing – Double Transfer Rate Figure 21: FAST READ Command – DTR Extended 0 7 8 Cx C LSB A[MIN] Command DQ0 MSB A[MAX] DQ1 DOUT High-Z LSB DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT MSB Dummy cycles Dual 0 3 4 Cx C LSB A[MIN] DOUT Command DQ[1:0] MSB A[MAX] LSB DOUT DOUT DOUT DOUT DOUT DOUT DOUT MSB Dummy cycles Quad 0 1 2 Cx C LSB A[MIN] DOUT Command D
PAGE 51
3V, 256Mb: Multiple I/O Serial Flash Memory READ MEMORY Operations Figure 22: DUAL OUTPUT FAST READ Command – DTR Extended 0 7 8 Cx C LSB DQ0 A[MIN] Command MSB DOUT LSB DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT A[MAX] High-Z DQ1 MSB Dummy cycles Dual 0 3 4 Cx C LSB A[MIN] DOUT Command DQ[1:0] MSB A[MAX] DOUT DOUT DOUT DOUT DOUT DOUT LSB DOUT MSB Dummy cycles Notes: 1. Cx = 7 + (A[MAX] + 1)/2. 2.
PAGE 52
3V, 256Mb: Multiple I/O Serial Flash Memory READ MEMORY Operations Figure 24: QUAD OUTPUT FAST READ Command – DTR Extended 0 7 8 Cx C LSB A[MIN] DOUT LSB DOUT DOUT DOUT High-Z DOUT DOUT DOUT DOUT ‘1’ DOUT DOUT DOUT DOUT Command DQ0 MSB A[MAX] DQ[2:1] DQ3 MSB Dummy cycles Quad 0 1 2 Cx C LSB A[MIN] DOUT Command DQ[3:0] MSB A[MAX] LSB DOUT DOUT DOUT MSB Dummy cycles Notes: 1. Cx = 7 + (A[MAX] + 1)/2. 2.
PAGE 53
3V, 256Mb: Multiple I/O Serial Flash Memory PROGRAM Operations PROGRAM Operations PROGRAM commands are initiated by first executing the WRITE ENABLE command to set the write enable latch bit to 1. S# is then driven LOW and held LOW until the eighth bit of the last data byte has been latched in, after which it must be driven HIGH. The command code is input on DQ0, followed by input on DQ[n] of address bytes and at least one data byte. Each address bit is latched in during the rising edge of the clock.
PAGE 54
3V, 256Mb: Multiple I/O Serial Flash Memory PROGRAM Operations Figure 26: PAGE PROGRAM Command Extended 0 7 8 Cx C LSB A[MIN] LSB Command DQ0 MSB A[MAX] Dual 0 3 DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN MSB 4 Cx C LSB A[MIN] LSB Command DQ[1:0] MSB A[MAX] Quad 0 1 DIN MSB 2 Cx C LSB A[MIN] LSB Command DQ[3:0] MSB A[MAX] DIN MSB 1. For extended SPI protocol, Cx = 7 + (A[MAX] + 1). Note: For dual SPI protocol, Cx = 3 + (A[MAX] + 1)/2.
PAGE 55
3V, 256Mb: Multiple I/O Serial Flash Memory PROGRAM Operations Figure 28: EXTENDED DUAL INPUT FAST PROGRAM Command Extended 0 7 8 Cx C LSB A[MIN] LSB Command DQ0 DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN MSB High-Z DQ1 A[MAX] Dual 0 3 MSB 4 Cx C A[MIN] LSB LSB Command DQ[1:0] MSB Note: A[MAX] DIN MSB 1. For extended SPI protocol, Cx = 7 + (A[MAX] + 1)/2. For dual SPI protocol, Cx = 3 + (A[MAX] + 1)/2.
PAGE 56
3V, 256Mb: Multiple I/O Serial Flash Memory PROGRAM Operations Figure 30: EXTENDED QUAD INPUT FAST PROGRAM Command Extended 0 7 8 Cx C LSB DQ0 A[MIN] LSB DIN DIN DIN High-Z DIN DIN DIN ‘1’ DIN DIN DIN DIN DIN Command MSB DQ[2:1] DQ3 A[MAX] Quad 0 1 MSB 2 Cx C LSB MSB Note: A[MIN] LSB Command DQ[3:0] A[MAX] DIN MSB 1. For extended SPI protocol, Cx = 7 + (A[MAX] + 1)/4. For quad SPI protocol, Cx = 1 + (A[MAX] + 1)/4. 09005aef84566603 n25q_256mb_65nm.pdf - Rev.
PAGE 57
3V, 256Mb: Multiple I/O Serial Flash Memory WRITE Operations WRITE Operations WRITE ENABLE Command The WRITE ENABLE operation sets the write enable latch bit. To execute a WRITE ENABLE command, S# is driven LOW and held LOW until the eighth bit of the command code has been latched in, after which it must be driven HIGH. The command code is input on DQ0 for extended SPI protocol, on DQ[1:0] for dual SPI protocol, and on DQ[3:0] for quad SPI protocol.
PAGE 58
3V, 256Mb: Multiple I/O Serial Flash Memory WRITE Operations Figure 31: WRITE ENABLE and WRITE DISABLE Command Sequence Extended 0 1 2 3 4 5 6 7 C S# Command Bits DQ0 0 0 0 0 0 LSB 1 1 0 MSB High-Z DQ1 Dual 0 1 3 2 C S# Command Bits DQ0 DQ1 LSB 0 0 1 0 0 0 0 1 MSB Quad 0 1 C S# Command Bits LSB DQ0 0 0 DQ1 0 1 DQ2 0 1 DQ3 0 0 Don’t Care MSB Note: 09005aef84566603 n25q_256mb_65nm.pdf - Rev. W 11/16 EN 1.
PAGE 59
3V, 256Mb: Multiple I/O Serial Flash Memory ERASE Operations ERASE Operations SUBSECTOR ERASE Command To execute the SUBSECTOR ERASE command and set the selected subsector bits set to FFh, the WRITE ENABLE command must be issued to set the write enable latch bit to 1. S# is driven LOW and held LOW until the eighth bit of the last data byte has been latched in, after which it must be driven HIGH. The command code is input on DQ0, followed by address bytes; any address within the subsector is valid.
PAGE 60
3V, 256Mb: Multiple I/O Serial Flash Memory ERASE Operations Figure 32: SUBSECTOR and SECTOR ERASE Command Extended 0 7 8 Cx C LSB DQ0 A[MIN] Command MSB Dual A[MAX] 0 3 4 Cx C LSB DQ0[1:0] A[MIN] Command MSB Quad A[MAX] 0 1 2 Cx C LSB MSB Note: A[MIN] Command DQ0[3:0] A[MAX] 1. For extended SPI protocol, Cx = 7 + (A[MAX] + 1). For dual SPI protocol, Cx = 3 + (A[MAX] + 1)/2. For quad SPI protocol, Cx = 1 + (A[MAX] + 1)/4.
PAGE 61
3V, 256Mb: Multiple I/O Serial Flash Memory ERASE Operations Figure 33: BULK ERASE Command Extended 0 7 C LSB Command DQ0 MSB Dual 0 3 C LSB Command DQ[1:0] MSB Quad 0 1 C LSB Command DQ[3:0] MSB PROGRAM/ERASE SUSPEND Command To initiate the PROGRAM/ERASE SUSPEND command, S# is driven LOW. The command code is input on DQ0. The operation is terminated by the PROGRAM/ERASE RESUME command.
PAGE 62
3V, 256Mb: Multiple I/O Serial Flash Memory ERASE Operations allowed during an ERASE SUSPEND state. When the ERASE operation resumes, it does not check the new lock status of the WRITE LOCK REGISTER command. During a PROGRAM SUSPEND operation, a READ operation is possible in any page except the one in a suspended state. Reading from a page that is in a suspended state will output indeterminate data.
PAGE 63
3V, 256Mb: Multiple I/O Serial Flash Memory ERASE Operations Table 29: Operations Allowed/Disallowed During Device States Note 1 applies to entire table Standby Operation State Program or Erase State Subsector Erase Suspend or Program Suspend State Erase Suspend State Notes READ Yes No Yes Yes 2 PROGRAM Yes No No Yes/No 3 ERASE Yes No No No 4 WRITE Yes No No No 5 WRITE Yes No Yes Yes 6 READ Yes Yes Yes Yes 7 SUSPEND No Yes No No 8 Notes: 1.
PAGE 64
3V, 256Mb: Multiple I/O Serial Flash Memory RESET Operations RESET Operations Table 30: Reset Command Set Command Command Code (Binary) Command Code (Hex) Address Bytes RESET ENABLE 0110 0110 66 0 RESET MEMORY 1001 1001 99 0 RESET ENABLE and RESET MEMORY Command To reset the device, the RESET ENABLE command must be followed by the RESET MEMORY command. To execute each command, S# is driven LOW. The command code is input on DQ0.
PAGE 65
3V, 256Mb: Multiple I/O Serial Flash Memory ONE TIME PROGRAMMABLE Operations ONE TIME PROGRAMMABLE Operations READ OTP ARRAY Command To initiate a READ OTP ARRAY command, S# is driven LOW. The command code is input on DQ0, followed by address bytes and dummy clock cycles. Each address bit is latched in during the rising edge of C. Data is shifted out on DQ1, beginning from the specified address and at a maximum frequency of fC (MAX) on the falling edge of the clock.
PAGE 66
3V, 256Mb: Multiple I/O Serial Flash Memory ONE TIME PROGRAMMABLE Operations The write enable latch bit is cleared to 0, whether the operation is successful or not, and the status register and flag status register can be polled for the operation status. When the operation completes, the write in progress bit is cleared to 0. If the operation times out, the write enable latch bit is reset and the program fail bit is set to 1.
PAGE 67
3V, 256Mb: Multiple I/O Serial Flash Memory ONE TIME PROGRAMMABLE Operations Figure 36: PROGRAM OTP Command Extended 0 7 8 Cx C LSB A[MIN] LSB Command DQ0 MSB A[MAX] Dual 0 3 DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN MSB 4 Cx C LSB A[MIN] LSB Command DQ[1:0] MSB A[MAX] Quad 0 1 DIN MSB 2 Cx C LSB A[MIN] LSB Command DQ[3:0] MSB A[MAX] Note: DIN MSB 1. For extended SPI protocol, Cx = 7 + (A[MAX] + 1).
PAGE 68
3V, 256Mb: Multiple I/O Serial Flash Memory ADDRESS MODE Operations – Enter and Exit 4-Byte Address Mode ADDRESS MODE Operations – Enter and Exit 4-Byte Address Mode ENTER or EXIT 4-BYTE ADDRESS MODE Command Both ENTER 4-BYTE ADDRESS MODE and EXIT 4-BYTE ADDRESS MODE commands share the same requirements. To enter or exit the 4-byte address mode, the WRITE ENABLE command must be executed to set the write enable latch bit to 1.
PAGE 69
3V, 256Mb: Multiple I/O Serial Flash Memory XIP Mode XIP Mode Execute-in-place (XIP) mode allows the memory to be read by sending an address to the device and then receiving the data on one, two, or four pins in parallel, depending on the customer requirements. XIP mode offers maximum flexibility to the application, saves instruction overhead, and reduces random access time.
PAGE 70
3V, 256Mb: Multiple I/O Serial Flash Memory XIP Mode Figure 37: XIP Mode Directly After Power-On Mode 3 C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mode 0 tVSI VCC (<100µ) NVCR check: XIP enabled S# A[MIN] DQ0 LSB DOUT DOUT DOUT DOUT DOUT Xb DOUT DOUT DOUT DOUT DOUT DQ[3:1] A[MAX] MSB Dummy cycles 1. Xb is the XIP confirmation bit and should be set as follows: 0 to keep XIP state; 1 to exit XIP mode and return to standard read mode.
PAGE 71
3V, 256Mb: Multiple I/O Serial Flash Memory XIP Mode Terminating XIP After a Controller and Memory Reset The system controller and the device can become out of synchronization if, during the life of the application, the system controller is reset without the device being reset. In such a case, the controller can reset the memory to power-on reset if the memory has reset functionality. (Reset is available in devices with a dedicated part number.
PAGE 72
3V, 256Mb: Multiple I/O Serial Flash Memory Power Up and Power Down Power Up and Power Down Power Up and Power Down Requirements At power-up and power-down, the device must not be selected; that is, S# must follow the voltage applied on V CC until V CC reaches the correct values: V CC,min at power-up and VSS at power-down. To avoid data corruption and inadvertent WRITE operations during power-up, a poweron reset circuit is included.
PAGE 73
3V, 256Mb: Multiple I/O Serial Flash Memory Initial Delivery Status Table 34: Power-Up Timing and VWI Threshold Note 1 applies to entire table Symbol Parameter Min Max Unit tVTR VCC,min to read – 150 µs tVTW VCC,min to device fully accessible – 150 µs VWI Write inhibit voltage 1.5 2.5 V 1. Parameters listed are characterized only.
PAGE 74
3V, 256Mb: Multiple I/O Serial Flash Memory AC Reset Specifications AC Reset Specifications Table 35: AC RESET Conditions Note 1 applies to entire table Parameter Symbol Reset pulse width Reset recovery time Software reset recovery time S# deselect to reset valid Conditions Min Typ Max Unit 50 – – ns Device deselected (S# HIGH) and is in XIP mode – – 40 ns Device deselected (S# HIGH) and is in standby mode – – 40 ns Commands are being decoded, any READ operations are in progress or an
PAGE 75
3V, 256Mb: Multiple I/O Serial Flash Memory AC Reset Specifications Figure 39: Reset AC Timing During PROGRAM or ERASE Cycle S# tSHRH tRHSL tRLRH RESET# Don’t Care Figure 40: Reset Enable 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 C Reset enable tSHSL2 tSHSL3 Reset memory S# DQ0 Figure 41: Serial Input Timing tSHSL S# tCHSL tSLCH tCHSH tSHCH C tDVCH tCHDX DQ0 DQ1 tCHCL tCLCH MSB in LSB in High-Z High-Z Don’t Care 09005aef84566603 n25q_256mb_65nm.pdf - Rev.
PAGE 76
3V, 256Mb: Multiple I/O Serial Flash Memory AC Reset Specifications Figure 42: Write Protect Setup and Hold During WRITE STATUS REGISTER Operation (SRWD = 1) W#/VPP tWHSL tSHWL S# C DQ0 DQ1 High-Z High-Z Don’t Care 09005aef84566603 n25q_256mb_65nm.pdf - Rev. W 11/16 EN 76 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2011 Micron Technology, Inc. All rights reserved.
PAGE 77
3V, 256Mb: Multiple I/O Serial Flash Memory AC Reset Specifications Figure 43: Hold Timing S# tCHHL tHLCH tHHCH C tHLQZ tCHHH tHHQX DQ0 DQ1 HOLD# Don’t Care 09005aef84566603 n25q_256mb_65nm.pdf - Rev. W 11/16 EN 77 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2011 Micron Technology, Inc. All rights reserved.
PAGE 78
3V, 256Mb: Multiple I/O Serial Flash Memory AC Reset Specifications Figure 44: Output Timing S# tCLQV tCLQV tCLQX tCLQX tCL tCH C tSHQZ DQ0 LSB out DQ1 Address LSB in Don’t Care Figure 45: VPPH Timing End of command (identified by WIP polling) S# C DQ0 tVPPHSL VPPH VPP 09005aef84566603 n25q_256mb_65nm.pdf - Rev. W 11/16 EN 78 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2011 Micron Technology, Inc. All rights reserved.
PAGE 79
3V, 256Mb: Multiple I/O Serial Flash Memory Absolute Ratings and Operating Conditions Absolute Ratings and Operating Conditions Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only. Exposure to absolute maximum rating for extended periods may adversely affect reliability. Stressing the device beyond the absolute maximum ratings may cause permanent damage.
PAGE 80
3V, 256Mb: Multiple I/O Serial Flash Memory Absolute Ratings and Operating Conditions Table 39: AC Timing Input/Output Conditions Symbol Description CL Load capacitance – Input rise and fall times Min Max Units Notes 30 30 pF 1 – 5 ns Input pulse voltages 0.2VCC to 0.8VCC V Input timing reference voltages 0.3VCC to 0.7VCC V Output timing reference voltages VCC/2 V Notes: VCC/2 2 1. Output buffers are configurable by user. 2. For quad/dual operations: 0V to VCC.
PAGE 81
3V, 256Mb: Multiple I/O Serial Flash Memory DC Characteristics and Operating Conditions DC Characteristics and Operating Conditions Table 40: DC Current Characteristics and Operating Conditions Parameter Symbol Input leakage current Test Conditions ILI Min Max Unit – ±2 µA Output leakage current ILO – ±2 µA Standby current ICC1 S = VCC, VIN = VSS or VCC – 100 µA Standby current ICC1 (automotive) 1 S = VCC, VIN = VSS or VCC – 250 µA ICC3 C = 0.1VCC/0.
PAGE 82
3V, 256Mb: Multiple I/O Serial Flash Memory AC Characteristics and Operating Conditions AC Characteristics and Operating Conditions Table 42: AC Characteristics and Operating Conditions Symbol Min Typ1 Max Unit Clock frequency for all commands other than READ (SPI-ER, QIO-SPI protocol) fC DC – 108 MHz Clock frequency for READ commands fR DC – 54 MHz Clock HIGH time tCH 4 – – ns 2 Clock LOW time tCL 4 – – ns 1 Clock rise time (peak-to-peak) tCLCH 0.
PAGE 83
3V, 256Mb: Multiple I/O Serial Flash Memory AC Characteristics and Operating Conditions Table 42: AC Characteristics and Operating Conditions (Continued) Symbol Min Typ1 Max Unit tWVCR – 40 – ns WRITE VOLATILE ENHANCED CONFIGURATION REGISTER cycle time tWRVECR – 40 – ns WRITE NONVOLATILE CONFIGURATION REGISTER cycle time tWNVCR – 0.2 3 s WRITE EXTENDED ADDRESS REGISTER cycle time tWREAR – 40 – ns tPP – 0.5 5 ms 7 PAGE PROGRAM cycle time (n bytes) – int(n/8) × 0.
PAGE 84
3V, 256Mb: Multiple I/O Serial Flash Memory Package Dimensions Package Dimensions Figure 47: V-PDFN-8/8mm x 6mm 0.15 C Pin 1 ID Ø0.3 4.80 TYP 0.15 C 6.00 TYP Pin 1 ID R 0.20 (NE - 1) × 1.27 TYP B 8 1 7 2 6 3 5 4 0.40 ±0.05 5.16 TYP 0.2 MIN 1.27 TYP +0.08 0.40 -0.05 0.10 M C A B 0.05 M C 8.00 TYP A 0.10 C 0.05 C 0.85 TYP/ 1 MAX 0.05 MAX Notes: 09005aef84566603 n25q_256mb_65nm.pdf - Rev. W 11/16 EN 1. All dimensions are in millimeters. 2.
PAGE 85
3V, 256Mb: Multiple I/O Serial Flash Memory Package Dimensions Figure 48: SOP2-16/300 mils 10.30 ±0.20 16 h x 45° 9 0.23 MIN/ 0.32 MAX 10.00 MIN/ 10.65 MAX 7.50 ±0.10 1 8 0° MIN/8° MAX 2.5 ±0.15 0.20 ±0.1 0.1 Z 0.33 MIN/ 0.51 MAX 1.27 TYP Notes: 09005aef84566603 n25q_256mb_65nm.pdf - Rev. W 11/16 EN 0.40 MIN/ 1.27 MAX Z 1. All dimensions are in millimeters. 2. See Part Number Ordering Information for complete package names and details. 85 Micron Technology, Inc.
PAGE 86
3V, 256Mb: Multiple I/O Serial Flash Memory Package Dimensions Figure 49: T-PBGA-24b05/6mm x 8mm 0.79 TYP Seating plane A 0.1 A Ball A1 ID 24X Ø0.40 ±0.05 5 4 3 2 Ball A1 ID 1 A B C 4.00 8 ±0.10 D 1.00 TYP E 1.20 MAX 1.00 TYP 4.00 0.20 MIN 6 ±0.10 Notes: 09005aef84566603 n25q_256mb_65nm.pdf - Rev. W 11/16 EN 1. All dimensions are in millimeters. 2. See Part Number Ordering Information for complete package names and details. 86 Micron Technology, Inc.
PAGE 87
3V, 256Mb: Multiple I/O Serial Flash Memory Part Number Ordering Information Part Number Ordering Information Micron Serial NOR Flash devices are available in different configurations and densities. Verify valid part numbers by using Micron’s part catalog search at micron.com. To compare features and specifications by device type, visit micron.com/products. Contact the factory for devices not found.
PAGE 88
3V, 256Mb: Multiple I/O Serial Flash Memory Part Number Ordering Information Table 44: Package Details Micron SPI and JEDEC Package Name Shortened Package Name V-PDFN-8/8mm x 6mm RP DFN-8/8mm Very thin, plastic small-outline, 8 terminal pads (no leads), 8mm x 6mm ME F8 MLP8, VDFPN8 SOP2-16/300 mil SO16W Small-outline integrated circuit, 16-pin, wide (300 mil) MF SF SO16W, SO16 SOIC-16/300 mil, wide 300 mil body SOP 16L 300 mil width T-PBGA-24b05/ 6mm x 8mm TBGA 24 Thin, plastic-ball grid arr
PAGE 89
3V, 256Mb: Multiple I/O Serial Flash Memory Revision History Revision History Rev. W – 11/16 • Change data byte for Read and Write extended address register • Added Initial Delivery Status Rev. V – 05/16 • Changed Typ PAGE PROGRAM cycle time (n bytes) Rev. U – 01/15 • Changed ICC1 (automotive) in the DC Current Characteristics and Operating Conditions table Rev. T – 03/14 • In Command Set table, updated value for Quad I/O FAST READ – DTR from 3Dh to 6Dh Rev. S – 11/13 • Added N25Q256A83ESFA0F Rev.
PAGE 90
3V, 256Mb: Multiple I/O Serial Flash Memory Revision History Rev. M – 09/12 • Added clarification notes to Signal Assignments Rev. L – 08/12 • Additional note to Command Set table in Command Definitions • Corrections to Commands in Command Definitions Rev. K – 07/12 • Added ICC1 (grade 3) to DC Characteristics and Operating Conditions • Removed READ FLAG STATUS related notes from Command Definitions • Added N25Q256A13EF8A0x, N25Q256A13ESFA0x, N25Q256A13ESFH0x, N25Q256A13E12A0x to Features Rev.
PAGE 91
3V, 256Mb: Multiple I/O Serial Flash Memory Revision History • Corrected timing diagram notes in READ MEMORY Operations • Corrected timing diagram notes in PROGRAM Operations • Changed WIP = 1 to WIP = 0 in Power-Up Timing diagram in Power Up and Power Down Rev. D – 05/11 • Micron rebrand Rev. C – 11/10 • Added Reset Enable; Read Extended Address Register, Dual I/O; Reset Enable and Reset Memory, Dual I/O; Read Extended Address Register, Quad I/O; Reset Enable and Reset Memory, Quad I/O Rev.