Datasheet

Device Protection

Table 3: Data Protection using Device Protocols

Note 1 applies to the entire table

Protection by: Description

Power-on reset and internal timer Protects the device against inadvertent data changes while the power supply is out-

side the operating specification.

Command execution check Ensures that the number of clock pulses is a multiple of one byte before executing a

PROGRAM or ERASE command, or any command that writes to the device registers.

WRITE ENABLE operation Ensures that commands modifying device data must be preceded by a WRITE ENABLE

command, which sets the write enable latch bit in the status register.

Note:

1. Extended, dual, and quad SPI protocol functionality ensures that device data is protec-

ted from excessive noise.

Table 4: Memory Sector Protection Truth Table

Note 1 applies to the entire table

Sector Lock Register

Memory Sector Protection Status

Sector Lock

Down Bit

Sector Write Lock

Bit

0 0 Sector unprotected from PROGRAM and ERASE operations. Protection status re-

versible.

0 1 Sector protected from PROGRAM and ERASE operations. Protection status rever-

sible.

1 0 Sector unprotected from PROGRAM and ERASE operations. Protection status not

reversible except by power cycle or reset.

1 1 Sector protected from PROGRAM and ERASE operations. Protection status not

reversible except by power cycle or reset.

Note:

1. Sector lock register bits are written to when the WRITE LOCK REGISTER command is exe-

cuted. The command will not execute unless the sector lock down bit is cleared (see the

WRITE LOCK REGISTER command). The sector lock register is programmed to have all

protection registers activated at power-up.

3V, 256Mb: Multiple I/O Serial Flash Memory

Device Protection

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n25q_256mb_65nm.pdf - Rev. W 11/16 EN

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