Datasheet

Figure 6: Bus Master and Memory Devices on the SPI Bus
SPI bus master
SPI memory
device
SDO
SDI
SCK
C
DQ1 DQ0
SPI memory
device
C
DQ1 DQ0
SPI memory
device
C
DQ1 DQ0
S#
CS3 CS2 CS1
SPI interface:
(CPOL, CPHA) =
(0, 0) or (1, 1)
W#
HOLD#
S#
W#
HOLD#
S#
W#
HOLD#
R R R
V
CC
V
CC
V
CC
V
CC
V
SS
V
SS
V
SS
V
SS
R
Figure 7: SPI Modes
C
C
DQ0
DQ1
CPHA
0
1
CPOL
0
1
MSB
MSB
3V, 256Mb: Multiple I/O Serial Flash Memory
Serial Peripheral Interface Modes
09005aef84566603
n25q_256mb_65nm.pdf - Rev. W 11/16 EN
18
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