Datasheet
Table 10: Nonvolatile Configuration Register Bit Definitions
Note 1 applies to entire table
Bit Name Settings Description Notes
15:12 Number of
dummy clock
cycles
0000 (identical to 1111)
0001
0010
.
.
1101
1110
1111
Sets the number of dummy clock cycles subse-
quent to all FAST READ commands.
The default setting targets the maximum al-
lowed frequency and guarantees backward com-
patibility.
2, 3
11:9 XIP mode at
power-on re-
set
000 = XIP: Fast Read
001 = XIP: Dual Output Fast Read
010 = XIP: Dual I/O Fast Read
011 = XIP: Quad Output Fast Read
100 = XIP: Quad I/O Fast Read
101 = Reserved
110 = Reserved
111 = Disabled (Default)
Enables the device to operate in the selected XIP
mode immediately after power-on reset.
8:6 Output driver
strength
000 = Reserved
001 = 90 Ohms
010 = 60 Ohms
011 = 45 Ohms
100 = Reserved
101 = 20 Ohms
110 = 15 Ohms
111 = 30 (Default)
Optimizes impedance at V
CC
/2 output voltage.
5 Reserved X "Don't Care."
4 Reset/hold 0 = Disabled
1 = Enabled (Default)
Enables or disables hold or reset.
(Available on dedicated part numbers.)
3 Quad I/O pro-
tocol
0 = Enabled
1 = Disabled (Default, Extended SPI prot-
cocol)
Enables or disables quad I/O protocol. 4
2 Dual I/O pro-
tocol
0 = Enabled
1 = Disabled (Default, Extended SPI pro-
tocol)
Enables or disables dual I/O protocol. 4
1 128Mb seg-
ment select
0 = Upper 128Mb segment
1 = Lower 128Mb segment (Default)
Selects a 128Mb segment as default for 3B ad-
dress operations. See also the extended address
register.
0 Address bytes 0 = Enable 4B address
1 = Enable 3B address (Default)
Defines the number of address bytes for a com-
mand.
Notes:
1. Settings determine device memory configuration after power-on. The device ships from
the factory with all bits erased to 1 (FFFFh). The register is read from or written to by
READ NONVOLATILE CONFIGURATION REGISTER or WRITE NONVOLATILE CONFIGURA-
TION REGISTER commands, respectively.
2. The 0000 and 1111 settings are identical in that they both define the default state,
which is the maximum frequency of
f
c = 108 MHz. This ensures backward compatibility.
3V, 256Mb: Multiple I/O Serial Flash Memory
Nonvolatile and Volatile Registers
09005aef84566603
n25q_256mb_65nm.pdf - Rev. W 11/16 EN
22
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