Datasheet

Table 12: Sequence of Bytes During Wrap
Starting Address 16-Byte Wrap 32-Byte Wrap 64-Byte Wrap
0 0-1-2- . . . -15-0-1- . . 0-1-2- . . . -31-0-1- . . 0-1-2- . . . -63-0-1- . .
1 1-2- . . . -15-0-1-2- . . 1-2- . . . -31-0-1-2- . . 1-2- . . . -63-0-1-2- . .
15 15-0-1-2-3- . . . -15-0-1- . . 15-16-17- . . . -31-0-1- . . 15-16-17- . . . -63-0-1- . .
31 31-16-17- . . . -31-16-17- . . 31-0-1-2-3- . . . -31-0-1- . . 31-32-33- . . . -63-0-1- . .
63 63-48-49- . . . -63-48-49- . . 63-32-33- . . . -63-32-33- . . 63-0-1- . . . -63-0-1- . .
Table 13: Supported Clock Frequencies – STR
Note 1 applies to entire table
Number of Dummy
Clock Cycles FAST READ
DUAL OUTPUT
FAST READ
DUAL I/O FAST
READ
QUAD OUTPUT
FAST READ
QUAD I/O FAST
READ
1 90 80 50 43 30
2 100 90 70 60 40
3 108 100 80 75 50
4 108 105 90 90 60
5 108 108 100 100 70
6 108 108 105 105 80
7 108 108 108 108 86
8 108 108 108 108 95
9 108 108 108 108 105
10 108 108 108 108 108
Note:
1. Values are guaranteed by characterization and not 100% tested in production.
Table 14: Supported Clock Frequencies – DTR
Number of Dummy
Clock Cycles FAST READ
DUAL OUTPUT
FAST READ
DUAL I/O FAST
READ
QUAD OUTPUT
FAST READ
QUAD I/O FAST
READ
1 45 40 25 30 15
2 50 45 35 38 20
3 54 50 40 45 25
4 54 53 45 47 30
5 54 54 50 50 35
6 54 54 53 53 40
7 54 54 54 54 43
8 54 54 54 54 48
9 54 54 54 54 53
10 54 54 54 54 54
3V, 256Mb: Multiple I/O Serial Flash Memory
Nonvolatile and Volatile Registers
09005aef84566603
n25q_256mb_65nm.pdf - Rev. W 11/16 EN
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