Datasheet
128Mb segmentation selection. If 4-byte addressing is enabled, extended address regis-
ter settings are ignored.
Enhanced Volatile Configuration Register
Table 16: Enhanced Volatile Configuration Register Bit Definitions
Note 1 applies to entire table
Bit Name Settings Description Notes
7 Quad I/O protocol 0 = Enabled
1 = Disabled (Default,
extended SPI protocol)
Enables or disables quad I/O protocol. 2
6 Dual I/O protocol 0 = Enabled
1 = Disabled (Default,
extended SPI protocol)
Enables or disables dual I/O protocol. 2
5 Reserved x = Default 0b = Fixed value.
4 Reset/hold 0 = Disabled
1 = Enabled (Default)
Enables or disables hold or reset.
(Available on dedicated part numbers.)
3 V
PP
accelerator 0 = Enabled
1 = Disabled (Default)
Enables or disables V
PP
acceleration for QUAD
INPUT FAST PROGRAM and QUAD INPUT EX-
TENDED FAST PROGRAM OPERATIONS.
2:0 Output driver strength 000 = Reserved
001 = 90 Ohms
010 = 60 Ohms
011 = 45 Ohms
100 = Reserved
101 = 20 Ohms
110 = 15 Ohms
111 = 30 (Default)
Optimizes impedance at V
CC
/2 output voltage.
Notes:
1. Settings determine the device memory configuration upon a change of those settings by
the WRITE ENHANCED VOLATILE CONFIGURATION REGISTER command. The register is
read from or written to in all protocols by READ ENHANCED VOLATILE CONFIGURATION
REGISTER or WRITE ENHANCED VOLATILE CONFIGURATION REGISTER commands, respec-
tively.
2. If bits 6 and 7 are both set to 0, the device operates in quad I/O. When either bit 6 or 7 is
reset to 0, the device operates in quad I/O or dual I/O respectively following the next
WRITE ENHANCED VOLATILE CONFIGURATION command.
Flag Status Register
Table 17: Flag Status Register Bit Definitions
Note 1 applies to entire table
Bit Name Settings Description Notes
7 Program or
erase
controller
0 = Busy
1 = Ready
Status bit: Indicates whether a PROGRAM, ERASE,
WRITE STATUS REGISTER, or WRITE NONVOLATILE CON-
FIGURATION command cycle is in progress.
2, 3
3V, 256Mb: Multiple I/O Serial Flash Memory
Nonvolatile and Volatile Registers
09005aef84566603
n25q_256mb_65nm.pdf - Rev. W 11/16 EN
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