Datasheet

Table 17: Flag Status Register Bit Definitions (Continued)
Note 1 applies to entire table
Bit Name Settings Description Notes
6 Erase suspend 0 = Not in effect
1 = In effect
Status bit: Indicates whether an ERASE operation has
been or is going to be suspended.
3
5 Erase 0 = Clear
1 = Failure or protection error
Error bit: Indicates whether an ERASE operation has
succeeded or failed.
4, 5
4 Program 0 = Clear
1 = Failure or protection error
Error bit: An attempt to program a 0 to a 1 when V
PP
=
V
PPH
and the data pattern is a multiple of 64 bits.
4, 5
3 V
PP
0 = Enabled
1 = Disabled (Default)
Error bit: Indicates an invalid voltage on V
PP
during a
PROGRAM or ERASE operation.
4, 5
2 Program sus-
pend
0 = Not in effect
1 = In effect
Status bit: Indicates whether a PROGRAM operation
has been or is going to be suspended.
3
1 Protection 0 = Clear
1 = Failure or protection error
Error bit: Indicates whether a PROGRAM operation has
attempted to modify the protected array sector or ac-
cess the locked OTP space.
4, 5
0 Addressing 0 = 3 bytes addressing
1 = 4 bytes addressing
Status bit: Indicates whether 3-byte or 4-byte address
mode is enabled.
3
Notes:
1. Register bits are read by READ STATUS REGISTER command. All bits are volatile.
2. These program/erase controller settings apply only to PROGRAM or ERASE command cy-
cles in progress; they do not apply to a WRITE command cycle in progress.
3. Status bits are reset automatically.
4. Error bits must be reset by CLEAR FLAG STATUS REGISTER command.
5. Typical errors include operation failures and protection errors caused by issuing a com-
mand before the error bit has been reset to 0.
3V, 256Mb: Multiple I/O Serial Flash Memory
Nonvolatile and Volatile Registers
09005aef84566603
n25q_256mb_65nm.pdf - Rev. W 11/16 EN
27
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