Datasheet

ManualsBrandsDIGILENT ManualsDev Kits410-340

Table 18: Command Set (Continued)

Note 1 applies to entire table

Command Code Extended

Dual

I/O

Quad

I/O

Data

Bytes Notes

SECTOR ERASE D8h Yes Yes Yes 0 4, 13

4-BYTE SECTOR ERASE DCh 4, 13, 14

BULK ERASE C7h Yes Yes Yes 0 4, 13

PROGRAM/ERASE RESUME 7Ah Yes Yes Yes 0 2, 13

PROGRAM/ERASE SUSPEND 75h

ONE-TIME PROGRAMMABLE (OTP) Operations

READ OTP ARRAY 4Bh Yes Yes Yes 1 to 64 5

PROGRAM OTP ARRAY 42h 4, 13

4-BYTE ADDRESS MODE Operations

ENTER 4-BYTE ADDRESS MODE B7h Yes Yes Yes 0 2, 16

EXIT 4-BYTE ADDRESS MODE E9h

QUAD Operations

ENTER QUAD 35h Yes Yes Yes 0 2, 14

EXIT QUAD F5h 2, 14

Notes:

1. Yes in the protocol columns indicates that the command is supported and has the same

functionality and command sequence as other commands marked Yes.

2. Address bytes = 0. Dummy clock cycles = 0.

3. Address bytes = 3. Dummy clock cycles default = 8.

4. Address bytes default = 3; address bytes = 4 (extended address). Dummy clock cycles = 0.

5. Address bytes default = 3; address bytes = 4 (extended address). Dummy clock cycles de-

fault = 8. Dummy clock cycles default = 10 (when quad SPI protocol is enabled). Dummy

clock cycles are configurable by the user.

6. Address bytes default = 3; address bytes = 4 (extended address). Dummy clock cycles de-

fault = 6. Dummy clock cycles default = 8 when quad SPI protocol is enabled. Dummy

clock cycles are configurable by the user.

7. Address bytes default = 3; address bytes = 4 (extended address). Dummy clock cycles de-

fault = 8. Dummy clock cycles are configurable by the user.

8. Address bytes = 4. Dummy clock cycles = 0.

9. Address bytes = 4. Dummy clock cycles default = 8. Dummy clock cycles default = 10

(when quad SPI protocol is enabled). Dummy clock cycles are configurable by the user.

10. Address bytes = 4. Dummy clock cycles default = 10. Dummy clock cycles is configurable

by the user.

11. When the device is in dual SPI protocol, the command can be entered with any of these

three codes. The different codes enable compatibility between dual SPI and extended

SPI protocols.

12. When the device is in quad SPI protocol, the command can be entered with any of these

three codes. The different codes enable compatibility between quad SPI and extended

SPI protocols.

13. The WRITE ENABLE command must be issued first before this command can be execu-

ted.

14. This command is only for part numbers N25Q256A83ESF40x, N25Q256A83E1240x, and

N25Q256A83ESFA0F.

3V, 256Mb: Multiple I/O Serial Flash Memory

Command Definitions

09005aef84566603

n25q_256mb_65nm.pdf - Rev. W 11/16 EN

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