Datasheet
Table 19: Lock Register (Continued)
Note 1 applies to entire table
Bit Name Settings Description
0 Sector write lock 0 = Cleared (Default)
1 = Set
Volatile bit: the device always powers-up with this bit cleared,
which means that PROGRAM and ERASE operations in this sector
can be executed and sector content modified.
When this bit is set, PROGRAM and ERASE operations in this sec-
tor will not be executed.
Note:
1. Sector lock register bits 1:0 are written by the WRITE LOCK REGISTER command. The
command will not execute unless the sector lock down bit is cleared.
Figure 12: READ LOCK REGISTER Command
MSB
DQ[0]
LSB
Command
A[MAX]
A[MIN]
7 8 C
x
0
C
3 4 C
x
0
C
MSB
DQ[1:0]
LSB
Command
A[MAX]
A[MIN]
MSB
D
OUT
D
OUT
D
OUT
D
OUT
D
OUT
LSB
1 2 C
x
0
C
MSB
DQ[3:0]
LSB
Command
A[MAX]
A[MIN]
MSB
D
OUT
D
OUT
D
OUT
LSB
Extended
Dual
Quad
High-Z
DQ1
MSB
D
OUT
D
OUT
D
OUT
D
OUT
D
OUT
LSB
D
OUT
D
OUT
D
OUT
D
OUT
Don’t Care
Note:
1. For extended SPI protocol, C
x
= 7 + (A[MAX] + 1).
For dual SPI protocol, C
x
= 3 + ((A[MAX] + 1)/2).
For quad SPI protocol, C
x
= 1 + ((A[MAX] + 1)/4).
WRITE LOCK REGISTER Command
To initiate the WRITE LOCK REGISTER command, the WRITE ENABLE command must
be executed to set the write enable latch bit to 1. S# is driven LOW and held LOW until
the eighth bit of the last data byte has been latched in, after which it must be driven
HIGH. The command code is input on DQn, followed by address bytes that point to a
location in the sector, and then one data byte that contains the desired settings for lock
register bits 0 and 1. Each address bit is latched in during the rising edge of the clock.
When execution is complete, the write enable latch bit is cleared within
t
SHSL2 and no
error bits are set. Because lock register bits are volatile, change to the bits is immediate.
WRITE LOCK REGISTER can be executed when an ERASE SUSPEND operation is in ef-
3V, 256Mb: Multiple I/O Serial Flash Memory
READ REGISTER and WRITE REGISTER Operations
09005aef84566603
n25q_256mb_65nm.pdf - Rev. W 11/16 EN
36
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