Datasheet

fect. If S# is not driven HIGH, the command is not executed, flag status register error
bits are not set, and the write enable latch remains set to 1.
Figure 13: WRITE LOCK REGISTER Command
7 8 C
x
0
C
MSB
DQ0
LSB
Command
A[MAX]
A[MIN]
MSB
D
IN
D
IN
D
IN
D
IN
D
IN
LSB
D
IN
D
IN
D
IN
D
IN
3 4 C
x
0
C
MSB
DQ[1:0]
LSB
Command
A[MAX]
A[MIN]
MSB
D
IN
D
IN
D
IN
D
IN
D
IN
LSB
1 2 C
x
0
C
MSB
DQ[3:0]
LSB
Command
A[MAX]
A[MIN]
MSB
D
IN
D
IN
D
IN
LSB
Extended
Dual
Quad
Note:
1. For extended SPI protocol, C
x
= 7 + (A[MAX] + 1).
For dual SPI protocol, C
x
= 3 + ((A[MAX] + 1)/2).
For quad SPI protocol, C
x
= 1 + ((A[MAX] + 1)/4).
CLEAR FLAG STATUS REGISTER Command
To execute the CLEAR FLAG STATUS REGISTER command and reset the error bits
(erase, program, and protection), S# is driven LOW. For extended SPI protocol, the com-
mand code is input on DQ0. For dual SPI protocol, the command code is input on
DQ[1:0]. For quad SPI protocol, the command code is input on DQ[3:0]. The operation
is terminated by driving S# HIGH at any time.
3V, 256Mb: Multiple I/O Serial Flash Memory
READ REGISTER and WRITE REGISTER Operations
09005aef84566603
n25q_256mb_65nm.pdf - Rev. W 11/16 EN
37
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.