Datasheet

Table 24: Parameter ID
Compliant with JEDEC standard JC-42.4 1775.03
Description
Address
(Byte Mode) Address (Bit) Data
Minimum block/sector erase sizes 30h 0 10
1
Write granularity 2 1
WRITE ENABLE command required for writing to volatile status reg-
isters
3 0
4
Reserved 5 1
6 1
7 1
4KB erase command code 31h 15:8 20h
Supports DUAL OUTPUT FAST READ operation (single input address,
dual output)
32h 16 1
Number of address bytes used (3-byte or 4-byte) for array READ,
WRITE, and ERASE commands
17 1
18
Supports double transfer rate clocking 19 1
Supports DUAL INPUT/OUTPUT FAST READ operation (dual input ad-
dress, dual output)
20 1
Supports QUAD INPUT/OUTPUT FAST READ operation (quad input
address, quad output)
21 1
Supports QUAD OUTPUT FAST READ operation (single input address,
quad output)
22 1
Reserved 23 1
Reserved 33h 31:24 FFh
Flash size (bits) 34h–37h 31:0 0FFFFFFFh
Number of dummy clock cycles required before valid output from
QUAD INPUT/OUTPUT FAST READ operation
38h 4:00 01001b
Number of XIP confirmation bits for QUAD INPUT/OUTPUT FAST
READ operation
7:5 001b
Command code for QUAD INPUT/OUTPUT FAST READ operation 39h 15:8 EBh
Number of dummy clock cycles required before valid output from
QUAD OUTPUT FAST READ operation
3Ah 20:16 00111b
Number of XIP confirmation bits for QUAD OUTPUT FAST READ op-
eration
23:21 001b
Command code for QUAD OUTPUT FAST READ operation 3Bh 31:24 6Bh
Number of dummy clock cycles required before valid output from
DUAL OUTPUT FAST READ operation
3Ch 4:0 01000b
Number of XIP confirmation bits for DUAL OUTPUT FAST READ oper-
ation
7:5 000b
Command code for DUAL OUTPUT FAST READ operation 3Dh 15:8 3Bh
3V, 256Mb: Multiple I/O Serial Flash Memory
READ IDENTIFICATION Operations
09005aef84566603
n25q_256mb_65nm.pdf - Rev. W 11/16 EN
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