Datasheet

Table 24: Parameter ID (Continued)
Compliant with JEDEC standard JC-42.4 1775.03
Description
Address
(Byte Mode) Address (Bit) Data
Number of dummy clock cycles required before valid output from
DUAL INPUT/OUTPUT FAST READ operation
3Eh 20:16 00111b
Number of XIP confirmation bits for DUAL INPUT/OUTPUT FAST
READ
23:21 001b
Command code for DUAL INPUT/OUTPUT FAST READ operation 3Fh 31:24 BBh
Supports FAST READ operation in dual SPI protocol 40h 0 1
Reserved 3:1 111b
Supports FAST READ operation in quad SPI protocol 4 1
Reserved 7:5 111b
Reserved 41h–43h – FFFFFFh
Reserved 44h–45h – FFFFh
Number of dummy clock cycles required before valid output from
FAST READ operation in dual SPI protocol
46h 4:0 00111b
Number of XIP confirmation bits for FAST READ operation in dual SPI
protocol
46h 7:5 001b
Command code for FAST READ operation in dual SPI protocol 47h 7:0 BBh
Reserved 48h–49h – FFFFh
Number of dummy clock cycles required before valid output from
FAST READ operation in quad SPI protocol
4Ah 4:0 01001b
Number of XIP confirmation bits for FAST READ operation in quad
SPI protocol
7:5 001b
Command code for FAST READ operation in quad SPI protocol 4Bh 7:0 EBh
Sector type 1 size (4k) 4Ch 7:0 0Ch
Sector type 1 command code (4k) 4Ch 7:0 0Ch
Sector type 2 size (64KB) 4Eh 7:0 10h
Sector type 2 command code 64KB) 4Fh 7:0 D8h
Sector type 3 size (not present) 50h 7:0 00h
Sector type 3 size (not present) 51h 7:0 00h
Sector type 4 size (not present) 52h 7:0 00h
Sector type 4 size (not present) 53h 7:0 00h
3V, 256Mb: Multiple I/O Serial Flash Memory
READ IDENTIFICATION Operations
09005aef84566603
n25q_256mb_65nm.pdf - Rev. W 11/16 EN
42
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