Datasheet

READ MEMORY Operations
The device supports default reading and writing to an A[MAX:MIN] of A[23:0] (3-byte
address).
Reading and writing to an A[MAX:MIN] of A[31:0] (4-byte address) is also supported. Se-
lection of the 3-byte or 4-byte address range can be enabled in two ways: setting the
nonvolatile configuration register or entering the ENABLE 4-BYTE ADDRESS MODE or
EXIT 4-BYTE ADDRESS MODE commands. Further details for these settings and com-
mands are in the respective register and command sections of the data sheet.
Note: When the device is set to the default address range of A[23:0], another method for
enabling 4-byte addressing is through the extended address register. Details can be
found in Nonvolatile and Volatile Registers.
3-Byte Address
To execute READ MEMORY commands, S# is driven LOW. The command code is input
on DQn, followed by input on DQn of three address bytes. Each address bit is latched in
during the rising edge of the clock. The addressed byte can be at any location, and the
address automatically increments to the next address after each byte of data is shifted
out; therefore, the entire memory can be read with a single command. The operation is
terminated by driving S# HIGH at any time during data output.
Table 25: Command/Address/Data Lines for READ MEMORY Commands
Note 1 applies to entire table
Command Name
READ
FAST
READ
DUAL OUTPUT
FAST READ
DUAL
INPUT/OUTPUT
FAST READ
QUAD OUTPUT
FAST READ
QUAD
INPUT/OUTPUT
FAST READ
STR Mode 03h 0Bh 3Bh BBh 6Bh EBh
DTR Mode 0Dh 3Dh BDh 6Dh EDh
Extended SPI Protocol
Supported Yes Yes Yes Yes Yes Yes
Command Input DQ0 DQ0 DQ0 DQ0 DQ0 DQ0
Address Input DQ0 DQ0 DQ0 DQ[1:0] DQ0 DQ[3:0]
Data Output DQ1 DQ1 DQ[1:0] DQ[1:0] DQ[3:0] DQ[3:0]
Dual SPI Protocol
Supported No Yes Yes Yes No No
Command Input DQ[1:0] DQ[1:0] DQ[1:0]
Address Input DQ[1:0] DQ[1:0] DQ[1:0]
Data Output DQ[1:0] DQ[1:0] DQ[1:0]
Quad SPI Protocol
Supported No Yes No No Yes Yes
Command Input DQ[3:0] DQ[3:0] DQ[3:0]
Address Input DQ[3:0] DQ[3:0] DQ[3:0]
3V, 256Mb: Multiple I/O Serial Flash Memory
READ MEMORY Operations
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n25q_256mb_65nm.pdf - Rev. W 11/16 EN
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