Datasheet

Figure 24: QUAD OUTPUT FAST READ Command – DTR
C
DQ0
DQ[2:1]
DQ3
Dummy cycles
7 8 C
x
0
MSB
LSB
Command
LSB
A[MAX]
High-Z
A[MIN]
‘1’
MSB
D
OUT
D
OUT
D
OUT
D
OUT
D
OUT
D
OUT
D
OUT
D
OUT
D
OUT
D
OUT
D
OUT
D
OUT
C
DQ[3:0]
Quad
Extended
1 2 C
x
0
MSB
LSB
Command
A[MAX]
A[MIN]
MSB
LSB
Dummy cycles
D
OUT
D
OUT
D
OUT
D
OUT
Notes:
1. C
x
= 7 + (A[MAX] + 1)/2.
2. Shown here is the QUAD OUTPUT FAST READ timing for the extended SPI protocol. The
quad timing shown for the FAST READ command is the equivalent of the QUAD OUT-
PUT FAST READ timing for the quad SPI protocol.
Figure 25: QUAD INPUT/OUTPUT FAST READ Command – DTR
C
DQ0
DQ[2:1]
Extended
DQ3
Dummy cycles
7 8 C
x
0
MSB
LSB
Command
LSB
High-Z
A[MIN]
‘1’
MSB
A[MAX]
D
OUT
D
OUT
D
OUT
D
OUT
D
OUT
D
OUT
D
OUT
D
OUT
D
OUT
D
OUT
D
OUT
D
OUT
C
DQ[3:0]
Quad
1 2 C
x
0
MSB
LSB
Command
A[MAX]
A[MIN]
MSB
LSB
Dummy cycles
D
OUT
D
OUT
D
OUT
D
OUT
Notes:
1. C
x
= 7 + (A[MAX] + 1)/8.
2. Shown here is the QUAD INPUT/OUTPUT FAST READ timing for the extended SPI proto-
col. The quad timing shown for the FAST READ command is the equivalent of the QUAD
INPUT/OUTPUT FAST READ timing for the quad SPI protocol.
3V, 256Mb: Multiple I/O Serial Flash Memory
READ MEMORY Operations
09005aef84566603
n25q_256mb_65nm.pdf - Rev. W 11/16 EN
52
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.